• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.6-13
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• 2006

In this paper, we studied vehicle to vehicle (VTV) communication system using DSRC of 5.8 GHz bands. Nowadays, in the road traffic system is going intelligent and advancing, communication between driving vehicle is very important technology for ITS. We can contrive smoothness and safety traffic flowing by exchanging information about velocity, location, braking and driving condition of nearby vehicles. Therefore, we developed and verified the system which required for the communication among vehicles using DSRC technology of 5.8 GHz band hasa 1 Mbps data rate in the high mobility condition. For this, we developed DSRC modem, data link layer and logic link layer to make it possible that communication between vehicles of perfectly operation, and developed application service program for VTV communication. We performed to communication test in the general road and ascent road. In case of the general mad, obtained VTV communication results are more than number of 17 with in 300 m LOS coverage, and total communication time are $2.34{\sim]18.7$ msec that considered maximum 8-transaction. We blow that obtained results can be used VTV communication or the in areas form the feasibility road test as a function or various conditions. In the future, this system is very useful of advanced safety vehicle (ASV) and super smart vehicle system (SSVS) and so on.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.107-115
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• 2011

In this paper, we proposed fast and efficient algorithm for detecting near-duplication based on content based retrieval in large scale video database. For handling large amounts of video easily, we split the video into small segment using scene change detection. In case of video services and copyright related business models, it is need to technology that detect near-duplicates, that longer matched video than to search video containing short part or a frame of original. To detect near-duplicate video, we proposed motion distribution and frame descriptor in a video segment. The motion distribution descriptor is constructed by obtaining motion vector from macro blocks during the video decoding process. When matching between descriptors, we use the motion distribution descriptor as filtering to improving matching speed. However, motion distribution has low discriminability. To improve discrimination, we decide to identification using frame descriptor extracted from selected representative frames within a scene segmentation. The proposed algorithm shows high success rate and low false alarm rate. In addition, the matching speed of this descriptor is very fast, we confirm this algorithm can be useful to practical application.

• Journal of Korea Spatial Information System Society
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• v.10 no.2
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• pp.1-12
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• 2008

Automatic semiconductor manufacture system generating transaction from 50,000 to 500,000 per a second needs storage management system processing very large data at once. A lot of storage management systems are researched for storing very large data. Existing storage management system is typical DBMS on a disk. It is difficult that the DBMS on a disk processes the 500,000 number of insert transaction per a second. So, the DBMS on main memory appeared to use memory. But it is difficultthat very large data stores into the DBMS on a memory because of limited amount of memory. In this paper we propose storage management system using insert transaction of a block unit that can process insert transaction over 50,000 and store data on low storage cost. A transaction of a block unit can decrease cost for a log and index per each tuple as transforming a transaction of a tuple unit to a block unit. Besides, the proposed system come cost to decompress all block of data because the information of each field be loss. To solve the problems, the proposed system generates the index of each compressed block to prevent reducing speed for searching. The proposed system can store very large data generated in semiconductor system and reduce storage cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.916-925
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• 2009

4S (Ship to Ship, Ship to Shore) communication is the key to strategic development of e-navigation, a core element of IT vessel convergence. 4S communication is intended to integrate and standardize various communication infrastructures on land and communication equipment complying with communication equipment equipped in ships. This paper aims to apply the Korean technology IEEE 802.16e adopted as an international standard, to replace and compensate for existing vessel communication media such as low speed HF/MF/VHF to the ocean environment. To this end, various experimental conditions between the coast station where a relay station was installed and related equipment equipped on a ship are set. Communication signals were monitored and the RSSI and CINR were measured. Based on experimental analysis and results, various challenges and solutions which may occur in ocean environment were sought, and communication availability was analyzed through transmission data throughput, at the maximum effective distance range of the signal. It was proven that high speed multimedia data could be exchanged for up to 20 km even among 80km kph ships moving around near the sea, ensuring that this technology could be applied to the ocean environment.

• Journal of Navigation and Port Research
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• v.33 no.10
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• pp.723-734
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• 2009

Container Vessel is becoming larger and faster thanks to the rapid growth of global trade and development of technology. Therefore, 15,000TEU vessel is expected to be ordered in near future. Every nations in north-east Asia are facing strong competition to be logistics hub to get the initiatives of logistics in response to the rapid change of logistics environment. According to the globalization of economy and major ports in this region also are trying to catch big shipping line for their survival. Considering above circumstances of the advent of ultra-large container vessel and spoke-and-hub strategy, it is inevitably necessary to make a fast and accurate vessel job in the terminal in order to be a leading port To meet this objective, current vessel planning system has to be improved innovatively. Therefore, this thesis propose multi distributed vessel planning system which enables multi loading/discharging planning with several planner simultaneously for faster and more accurate than existing planning and enhances quality of planning through information sharing among planners. Also this thesis uses simulation through Arena to verify the efficiency of this multi-distributed vessel planning system.

• Journal of Navigation and Port Research
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• v.33 no.10
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• pp.691-697
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• 2009

Hardware dedicated off-the-shelf maritime differential GPS RSIM lacks the open architecture to meet all the minimum maritime user requirements and to include future GNSS improvements after recapitalization. This paper carries out a study to replace existing hardware dedicated differential GPS RSIM with software differential GPS RSIM in order to make up the weak point of hardware dedicated off-the-shelf maritime differential GPS RSIM. In this paper, the architecture of software RSIM is proposed for maritime DGPS recapitalization. And the feasibility analysis of the proposed software differential GPS RSIM is performed as the first phase to realize the proposed architecture. For the feasibility analysis, the prototype RF module and DSP module are implemented with properties as wide RF bandwidth, high sampling frequency, and high speed transmission interface. This paper shows that the proposed architecture has the possibility of real time operation of software RSIM functionality onto the PC-based platform through the analysis of computation time. Finally, this paper verifies that the L1/L2 dual frequency software differential RSIM designed according to the proposed method satisfies the performance specifications set out in RTCM paper 221-2006-SC104-STD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.447-452
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• 2020

The purpose of this research was to confirm that prefrontal neurofeedback training has an impact on adolescents. The objective of this study was to prove its scientific effect through experimentation. The effect of the training was measured by the difference in neuro?frequencies before and after the training. For this research, an experimental group and a control group, each with 22 students in J High School located in the city of S participated in this study. From May to July 2019, the training was conducted three times a week and for 30 minutes per session. The neuro?frequency data collected were analyzed through the methods of F.F.T. The resulting changes from the neurofeedback training for each group were analyzed by T-Tests. The result of the study is as follows; Neurofeedback training has had a positive effect on adolescent attention and sleep. In conclusion, the environmental and educational factors also play an important role. As the interaction of the latter two factors yield an individual's unique brain structure and functionality, the impact of the neurofeedback training is important on adolescents. The derivation of the above results by utilizing scientific and objective methods reemphasizes the importance of this study.