• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.941-950
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• 1991

channel is severely degraded by multipath delay time spread. In this paper. We propose a simple multipath delay time detection method, which has a merit of in serviceable, yet simple H/W realizability for $\pi/4$ shift QPSK by detecting cross channel interference. A $\pi/4$ shift QPSK signal originally has quadrature channel(Q-ch) component. Thus in order to measure CCI between in-phase channel(I-ch) and quadrature channel(Q-ch), which closely related to multipath delay time, Frequency doubling scheme(frequency doubler) and differential detector is proposed, which makes $\pi/4$ shift QPSK signal look like BPSK and also makes it possible for CCI to be detected at I-ch detector output. To get an information from time varying I-ch output signal under the multipath lading environment, a method for obtaining the mean of the absolute value$(V_{MABS}(t))$ and another one for obtaining the root mean square value$(V_{RMS}(t))$ of CCI are proposed. Furthermore, a relationship between delay spread and CCI is also analyzed. In order to confirm theoretical results, computer simulation has been carried out under the quasi-static and Reyleigh distributed two ray multipath fading environments. A fairly good result was obtained. However it was also shown that this method is sensitive to bandwidth restriction to some extent. In addition, some idea for a simple hardware realization for the frequency doubler are given.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.1
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• pp.116-124
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• 2009

This paper proposes a new Artificial-Intelligent(AI) Power Quality(PQ) diagnosis algorithm using Discrete Wavelet Transform(DWT), Fast Fourier Transform(FFT), Root-Mean-Square(RMS) value. The developed algorithm is able to detect and classify the PQ problems such as the transient, the voltage sag, the voltage swell, the voltage interruption and the total harmonics distortion. The 15.36[kHz] sampling frequency is used to measure the voltages in a power system. The measured signals are used for DWT, FFT, RMS calculation. For AI diagnosis of the PQ problems, a simple multi-layered Artificial Neural Network(ANN) with the back-propagation algorithm is adopted, programmed in C++ and tested in PSIM simulation studies. Finally, the algorithm, which is installed in MP PQ+256 with TI DSP320C6713, is proved to diagnose the PQ problems efficiently.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.4
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• pp.300-309
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• 1996

The electric and magnetic fields radiated by lightning discharges are significantly changeable in amplitude and time, one of the topics concerning electromagnetic compatibility of modern electronic systems is the efficient and economic protection against transient voltages caused by not only by direct but also by nearly lightning strokes. In this paper, in order to obtain the detailed informations about lightning electromagnetic impulse waveforms, the electric and magnetic fields radiated by lightning discharges in the summer of 1995 were measured by a fast electric antenna and a loop-type magnetic field sensor, and their charac- teristics were presented and analyzed. The signals of the electric and magnetic fields were re- corded continuously by a transient digitizer having a resolution of 12 bit and a memory capacity of 5000 point and using a sampling time of 200 ns. The electric and magnetic field waveforms associated with lightning return strokes are significantly different with those of intracloud discharges. The magnetic fields radiated by intracloud lightning discharges have essentially the same waveforms as the electric field when the lightning discharhes are at distance of 50 km or more. Also the main frequency components of the electric and magnetic fields radiated by lightning discharges range from a few kHz to several hundred kHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1253-1259
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• 2005

This paper dealt with the development of surge protection devices (SPDs) that can protect high speed computer network devices from overvoltages caused by switching operations or lightning surges. The designed SPD is a form of hybrid circuit which is composed of a gas tube having large current diverting capability, high response bi-directional avalanche diodes, and fast recovery diodes to reduce insertion loss on high frequency domain. Surge protection and signal transmission characteristics of the fabricated SPD was tested according to the international standards, IEC 61000-4-5 and IEC 61643-21. From the test results, the SPD is satisfied with the international standards and the high cut-off frequency was 204 MHz. Also, the SPD showed a good performance without an insertion loss on a field test of 100 Mbps class Local Area Network.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.8
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• pp.801-806
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• 2015

Journal bearings support rotors using fluid film between the rotor and the stator. Generally, journal bearings are used in large rotor systems such as turbines in a power plant, because even in high-speed and load conditions, journal bearing systems run in a stable condition. To enhance the reliability of journal-bearing systems, in this paper, we study health-diagnosis algorithms that are based on the supervised learning method. Specifically, this paper focused on defining the unit of features, while other previous papers have focused on defining various features of vibration signals. We evaluate the features of various lengths or units on the separable ability basis. From our results, we find that one cycle datum in the time-domain and 60 cycle datum in the frequency domain are the optimal datum units for real-time journal-bearing diagnosis systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.60-67
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• 2010

We designed Average Current Control PFC IC which has make the average value of boost inductor current became the shape of sine wave. Designed IC has fixed frequency of 75kHz to meet EMI standard requirement. And also RC compensation loop has been designed into the error amp and the current amp, in order that it has wide bandwidth for high speed control. And we use the oscillator which generates by square wave and triangle wave, and add to UVLO, OVP, OCP, TSD which is in order to operate stability. We simulated by using Spectre of Cadence to verify the unity power factor function and various protection circuits and fabricated in a $1{\mu}m$ High Voltage(20V) CMOS process.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.9-16
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• 1996

This paper deals with the capacitive voltage divider which can measure a transient voltages generated by operating a high voltage impulse generator. The transient voltage measuring system using the capacitive electric field sensor consists of the planar-type electric field sensor having a fast response characteristic and the wide-bandwidth voltage follower, and the input impedance of which is extremely high, about $10^{12}{\Omega}$. In order to analyze the response characteristics to a step input, the newly developed calibration method is proposed, and the error of voltage dividing ratio associated with set-up condition is investigated. Also the optimal set-up condition that is to be maintained within the range of 0.5 % is taken. From the calibration experiment, the frequency bandwidth of the transient voltage measuring system whose response time to a step input is about 15.8 ns, is from 6.37 Hz to 27.3 MHz. Therefore it is possible to measure the commercial frequency voltages as well as the transient over voltages without signal distortions.