• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.1-7
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• 2010

PAPR of the pilot symbols can be reduced down by the CAZAC sequence in the SC-FDMA communication system. However, it is very complicated and takes quite a long time to compute the interpolation between the OFDM information symbols for the channel estimation because the pilot data are trasmitted in the block type. Furthermore, situation will be much more serious in the severe fading channel. Actually the pilot insertion of the comb type is much efficient and convenient for the channel estimation since the calculation of the interpolation can be made in the frequency domain symbol by symbol. But, the PAPR will be regrown when the pilot data are inserted with the information data in the comb type. So, in this paper, we like to study the PAPR reduction and comb type pilot assignment for the efficient channel estimation. Unlike the conventional SLM(selected mapping) method requiring the side information, our improved SLM method is to use the phase rotation sequence into information data without rotating phase of pilot. We use different pilot data according to the different phase rotation sequence. From the simulation result, it can be confirmed that when SLM method of 4 phase rotation sequence is used, PAPR is almost same to the block type method without pilot.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.10
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• pp.324-329
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• 2018

This study examined the effects of the contact position and structure of the test probe on its signal transmission characteristics. The contact position in the operating of the test probe was considered and then divided into the plunger inner contact and barrel inlet contact. The high frequency performance of the test probes was investigated for both contact positions. The signal transmission characteristics of the test probes with the structures of double, single, and out-spring was also analyzed. The insertion and return losses were calculated using the HFSS and the characteristic impedance of the test probes was analyzed using a Q3D simulation. The insertion loss of the barrel inlet contact was smaller than that of the plunger inner contact. The contact position of the test probe may result in a change in the high frequency performance. The out-spring probe has better frequency characteristics at -1 dB insertion loss and -10 dB return loss. The double probe and single probe have the same characteristic impedance with $30.8{\Omega}$. On the other hand, the out-spring probe has an impedance of $47.1{\Omega}$. The out-spring probe is closer to $50{\Omega}$ than the other probes and then shows higher signal transmission characteristics. The out-spring probe has superior high-frequency characteristics and is expected to be suitable for high-speed applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.130-133
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• 2002

As a society advances, an aging phenomenon and many diseases which did not exist in old times are happening. Especially, in case of the aged patient, because we cant know the time the condition of the patients health become worse, the study of the Tele-information system has been actively carried out by the necessity of a persistent observation. A ECG signal a kind of a vital signals has been widely used to the medical information system as an usual clinical diagnosis for the patients who possess heart diseases. BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self - error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, It will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the small size is present According to this, Bluetooth module transmits the medical information, which is input from the outside among the operations that use the Bluetooth to the Bluetooth module that is connected the host PC. And the system that the host PC transmits the medical information from the connected Bluetooth module to the Internet has once embedded. this study let the host PC embedded in advance of the existing system and transmit the medical information by the addition of the Tcp/Ip protocol stark under all embedded environments to internet.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2C
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• pp.132-140
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• 2007

In this paper, we proposed a new technique to encode and decode the digital hologram. Since the digital hologram (or fringe pattern) is generated by interference of light, it has much different property from natural 2D (2 dimensional) images. First, we acquisite optical-sensed or computer-generated hologram by digital type, and then extract a chrominance component. The extracted digital hologram for coding is separated into segments to use multi-view properties. The segmented hologram shows the similar characteristics with picturing an object with 2D cameras in various point of view. Since fringe pattern is visually observed like as noise, we expect that the fringe pattern has poor coding efficiency. To obtain high efficiency, the segment is transformed with DCT (Discrete Cosine Transform) which resembles hologram generation process with high performance. Each transformed segment passes the 3D scanning process according to time and spatial correlation, and is organized into a video stream. Since the segment which correspond to frame of a video stream consists of the transformed coefficients with wide range of value, it is classified and re-normalized. Finally it is compressed with coding tools. The proposed algorithm illustrated that it has better properties for reconstruction of 16 times higher compression rate than the previous researches.

• Economic and Environmental Geology
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• v.38 no.2 s.171
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• pp.155-163
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• 2005

For an unbiased TF (Tansfer Function) estimations we investigate geomagnetic TF derived from ICHEON and YONGIN sites, employing RR (Remote Reference) and SNS (Signal Noise Separation) techniques. The Rh technique, which requires synchronized field variations recorded at a clean remote site, is a reliable method to minimize the bias of TF by uncorrelated noises in magnetic channels. Meanwhile, SNS technique based on the assumption of noise-free remote data can improve the signal-noise level by separating signal TF and noise TF, which is successfully applied to the environments with strong correlated noises. In this study, TF at YONGIN is analyzed using geomagnetic data from ICHEON site as a remote reference, which seem to have somewhat better data quality. The application of Rh technique reduces the bias of TF, which appears in single site robust estimation, and makes curves in the amplitude and phase of TF more smooth as frequency. Futhermore, in order to investigate noise source quantitatively, SNS technique is applied. The results of SNS suggest that dominant noise source seems to be located at western region of YONGIN. This noise source is considered to originate from railway system such as KTX and national subway. which passes through the west regions of YONGIN.

• Journal of Korean Tunnelling and Underground Space Association
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• v.15 no.3
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• pp.187-199
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• 2013

Umbrella arch method (UAM) used for improving the stability of the tunnel ground condition has been widely applied in the tunnel construction projects due to the advantage of obtaining both reinforcement and waterproof. The purpose of this study is to develop the evaluation technique of the integrity of bore-hole in UAM by using a non-destructive test and to evaluate the possibility of being applied to the field. In order to investigate the variations of frequency depending on grouted length, the specimens with different grouted ratios are made in the two constraint conditions (free boundary condition and embedded condition). The hammer impact reflection method in which excitation and reception occur simultaneously at the head of pipe was used. The guided waves generated by hitting a pipe with a hammer were reflected at the tip and returned to the head, and the signals were received by an acoustic emission (AE) sensor installed at the head. For the laboratory experiments, the specimens were prepared with different grouted ratios (25 %, 50 %, 75 %, 100 %). In addition, field tests were performed for the application of the evaluation technique. Fast Fourier transform and wavelet transform were applied to analyze the measured waves. The experimental studies show that grouted ratio has little effects on the velocities of guided waves. Main frequencies of reflected waves tend to decrease with an increase in the grouted length in the time-frequency domain. This study suggests that the non-destructive tests using guided ultrasonic waves be effective to evaluate the bore-hole integrity of the UAM in the field.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.