• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.72-73
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• 2007

기존의 공정자동화 설비에서는 센서를 통하여 계측된 데이터들이 4-20mA의 아날로그 신호를 통하여 제어기와 컴퓨터들로 전송되었다. 이러한 아날로그 신호 전송 방식에서는 제어 시스템의 구조가 복잡해지고 설치에 많은 비용과 노력이 투입될 수밖에 없다. 이러한 문제점을 해소하기 위하여 기술 선진국에서는 필드 장비들 간에 고속의 직렬 통신을 통하여 제어 및 자동화 관련 디지털 데이터의 전송을 실시간으로 지원하는 필드버스 통신망을 개발하였으며, 1990년대 이후 공장 자동화, 공정 제어 및 발전 설비 등 각종 산업 설비에 필드버스를 매우 활발히 도입하고 있다. Foundation Fieldbus 모듈은 공정제어 시스템예서 사용되는 센서, 제어기, PLC, 밸브, 구동기, 스위치 등의 모든 필드 장비에 바로 탑재되어 Foundation Fieldbus의 통신 기능을 제공하는 통신 부품으로 첨단의 공정자동화 시스템을 구축하기 위하여 반드시 확보되어야 할 핵심기술이다. 본 연구를 통해 제작된 Foundation Fieldbus 모듈은 기존의 센서제품을 FF기반의 지능형 센서로 바로 전환할 수 있는 핵심부품이다.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.13-16
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• 2014

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.15-19
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• 2013

Lithium-ion batteries have been used for high density energy storage system due to the features such as low self-discharge rate. And the unit cell battery with the voltage less than 4V is recommended to use the series connections for a high voltage charger. When batteries are charged or discharged with series connection, there may be an explosion or degradation of unit cell battery owing to undistributed internal resistance of cell battery. therefore, the voltages of unit cell batteries should be monitored to prevent an overcharging and a deep discharging. This paper introduces the implementation of CVM (Cell Voltage Monitoring) system that can transmit the 12 channel's information including voltages and temperatures with the 12-bits resolutions and the transmission speed of 192 kbps.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.499-500
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• 2008

기존 칩들 사이에 사용되는 인터페이스는 많은 선을 사용하여 EMI문제를 발생시키고 PCB에 많은 중간을 차지한다. 이를 해결하기 위하여 개발된 UniPro는 적은 선으로 빠른 통신속도를 지원하며 저전력 통신을 위하여 D-PHY와 함께 사용된다. 본 논문에서는 MIPI 규격의 UniPro를 설계하였다. 설계된 UniPro는 4개의 데이터 레인과 1개의 클럭 레인으로 구성하여 디바이스 사이의 데이터 및 제어신호를 전송 가능하다. 또한 낮은 전력소모를 위하여 전원 관리 장치를 추가하였으며 수신한 데이터의 에러검출이 가능하도록 설계하여 신뢰도를 높였다. 설계된 인터페이스는 5,160 Gate크기이며 속도는 98MHz이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.590-597
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• 2002

Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.