• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.1
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• pp.26-32
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• 1997

In this paper, numerical analysis of dynamic characteristics for the plunger-type solenoid was used for a high speed solenoid valve with fast switching is discussed. The theoretic analysis of the electromagnetic field including eddy currents in the solenoid is studied by using permeance. The optimum value of design parameters which are a mass and an area of the plunger, a source voltage, a elastic modulus of the spring, a stroke, a number of turns, are obtained by the results of the investigation on effect of a parameter on others. And dynamic characteristics of acting solenoid that is the variation of magnetic force, displacement, solenoid current are investigated.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.3
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• pp.234-240
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• 2007

In this paper, a novel multi-level inverter for low cost high speed switched reluctance(SR) drive is proposed. The proposed multi-level converter has reduced number of power switches and diodes than that of a conventional asymmetric converter for SRM and smaller voltage rating of the dump capacitor comparing with energy efficient c-dump converter. It can supply five operating modes that is boosted, DC-link, zero, negative bias and negative boosted voltage. The proposed multi-level converter has fast excitation and demagnetization modes of phase current, so dynamic response can be achieved. The proposed multi-level converter is verified by computer simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.227-228
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• 2014

열차가 주행하는 선로에 설치되는 궤도회로는 레일 자체를 전기회로의 일부로 사용하여 일정 구간 내의 차량 유무를 판단하기 위한 회로이다. 국내의 경우 사용 주파수에 따라 전원전압 주파수의 짝수 고조파 대역을 사용하는 고속선 궤도회로와 홀수 고조파 대역을 이용하는 일반선 궤도회로로 구분할 수 있다. 이러한 궤도회로가 설치된 선로를 주행하는 고속차량의 주전력변환장치 컨버터는 단위 역률 제어를 수행하기 위하여 전원전압의 홀수 배수의 스위칭 주파수를 가지고 있기 때문에 컨버터 동작 시 가선전류에 고조파 전류가 생성된다. 이 때 컨버터부에서 발생되는 고조파 전류의 주파수와 궤도회로의 사용 주파수 대역이 일치하는 경우에 궤도회로의 오작동을 유발할 수 있다. 본 논문에서는 입력 컨버터부에서 사용하는 스위칭 주파수를 운행 구간에 따라 가변시켜 궤도회로 간섭 고조파 성분을 제어하는 방법을 제안하고 시험을 통해 성능을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.69-77
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• 2005

The Viterbi decoder which is used for the forward error correction(FEC) is a crucial component for successful modern communication systems. As modern communication speed rapidly high, the development of high speed communication module is important. However, since the feedback loop in ACS operation, high speed of Viterbi decoder is very difficult. In this paper, we propose an area reduced, high speed ACS Architecture of Viterbi decoder based on the radix-4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming of path metric memory. The proposed ACS architecture of Viterbi decoder is implemented in VHDL and synthesized in Xilinx ISE 6.2i. The area-time product of the proposed architecture is improved by 11% compared to that of the previous high speed radix-4 ACS architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.885-892
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• 2017

In this paper, we proposed a novel crowbar circuit for high-speed discharge charge switching to solve discharge charge-time delay of supply voltage in the conventional crowbar circuit. The proposed circuit is designed to increase the charge-speed after high-speed discharge of supply voltage, thereby reducing the time exposed to radiation damage and, the normal operation time of electronic system after passing the pulse radiation. The simulation of the discharge charge-times before the implement of the hardware is conducted using Cadence's pspice tool, and DUT (Device Under Test) board is fabricated in the device level. The comparison measurement of the crowbar circuits is performed on the satellite-electronic device for 24V. As the result, we confirmed the high-speed function of the proposed circuit by improvement of the discharge-speed 96.8% and the charge-speed 27.3% as compared with the conventional circuit.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.1-8
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• 2008

Shack-Hartmann sensors are widely employed as a wavefront measuring device in various applications. Adaptive optics is one of the major applications. Since an adaptive optics system should be operated in real-time, high-speed wavefront sensing is essential. In high-speed operation, integration time of an image detector is very short. In this case, noises such as readout noise and photon noise greatly influence the accuracy of wavefront sensing. Therefore a fast and noise-insensitive centroid finding algorithm is required for the real-time wavefront sensing. In this paper, the multi-resolution correlation method is proposed. By employing multi-resolution images, this method greatly reduces the computation time when compared to the fast Fourier transform (FFT) correlation method. The verification is performed through the computational simulation. In this paper, the center of mass method, correlation method and multi-resolution correlation method are employed to compare the measurement accuracy of the centroid finding algorithms. The accuracy of a Shack-Hartmann wavefront sensor using the proposed algorithm is proved to be comparable to that of the conventional correlation method.

• Journal of IKEEE
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• v.27 no.4
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• pp.601-609
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• 2023

In this paper, we propose an artificial intelligence-based high-speed fault diagnosis method using an FPGA in the event of a ground fault in a DC system. When applying artificial intelligence algorithms to fault diagnosis, a substantial amount of computation and real-time data processing are required. By employing an FPGA with AI-based high-speed fault diagnosis, the DC breaker can operate more rapidly, thereby reducing the breaking capacity of the DC breaker. therefore, in this paper, an intelligent high-speed diagnosis algorithm was implemented by collecting fault data through fault simulation of a DC system using Matlab/Simulink. Subsequently, the proposed intelligent high-speed fault diagnosis algorithm was applied to the FPGA, and performance verification was conducted.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.747-750
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• 2008

JPEG(Joint Photographic Expert Group)은 손실 압축 기법을 사용하여 데이터 양을 20:1 이상으로 현저히 줄이면서도 원 영상과 거의 유사한 영상을 복원할 수 있도록 해주기 때문에, 요즘 디지털 카메라 및 휴대폰 등 영상을 저장할 매 대부분 Exif(Exchangeable image file format)로 JPEG 압축형식을 널리 사용하고 있다. 본 논문은 JPEG 베이스라인 모드로 압축되어진 영상의 디코딩 단계에서 필요한 비계층형 헤더를 파싱하는 모듈의 기능을 소프트웨어로 모델링하고 VHDL을 이용하여 회로를 합성하고 동작을 검증하였다. 설계 결과 Xilinx xc3s1000 fg676-4 환경에서 154.488MHz의 동작속도를 나타내었고, JPEG 디코더의 고속 데이터 처리에 적응 가능하다.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.44-45
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• 2013

본 논문은 3상 PMSM 동작 중 한 개의 상이 고장이 났을 경우, 2상을 통하여 고장허용 동작을 하는데 있어서 발생하는 토크 리플 저감 방법에 대하여 연구를 하였다. 기존의 방법들이 기본파 주파수로 회전하는 동기좌표계상에서 전향 보상 방식으로 교류 성분의 전류를 제어함으로써 토크 리플을 보상하는 데에 반해 제안한 방법은 기본파 주파수의 2배수로 회전하는 동기좌표계상에서 직류 성분의 전류로 토크 리플을 보상하기 때문에, 저속 운전뿐만 아니라 고속 운전시에도 그 보상 특성이 매우 우수하다. 제안한 방법은 자동차용 전동식 조향 시스템에 적용하여 그 유효성을 실험적으로 검증하였다.