• 한국재료학회지
• /
• 제21권5호
• /
• pp.243-249
• /
• 2011

To reduce manufacturing costs of crystalline silicon solar cells, silicon wafers have become thinner. In relation to this, the properties of the aluminium-back surface field (Al-BSF) are considered an important factor in solar cell performance. Generally, screen-printing and a rapid thermal process (RTP) are utilized together to form the Al-BSF. This study evaluates Al-BSF formation on a (111) textured back surface compared with a (100) flat back surface with variation of ramp up rates from 18 to $89^{\circ}C$/s for the RTP annealing conditions. To make different back surface morphologies, one side texturing using a silicon nitride film and double side texturing were carried out. After aluminium screen-printing, Al-BSF formed according to the RTP annealing conditions. A metal etching process in hydrochloric acid solution was carried out to assess the quality of Al-BSF. Saturation currents were calculated by using quasi-steady-state photoconductance. The surface morphologies observed by scanning electron microscopy and a non-contacting optical profiler. Also, sheet resistances and bulk carrier concentration were measured by a 4-point probe and hall measurement system. From the results, a faster ramp up during Al-BSF formation yielded better quality than a slower ramp up process due to temperature uniformity of silicon and the aluminium surface. Also, in the Al-BSF formation process, the (111) textured back surface is significantly affected by the ramp up rates compared with the (100) flat back surface.

• 한국재료학회지
• /
• 제27권10호
• /
• pp.518-523
• /
• 2017

In commercial solar cells, the pattern of the front electrode is critical to effectively assemble the photo generated current. The power loss in solar cells caused by the front electrode was categorized as four types. First, losses due to the metallic resistance of the electrode. Second, losses due to the contact resistance of the electrode and emitter. Third, losses due to the emitter resistance when current flows through the emitter. Fourth, losses due to the shading effect of the front metal electrode, which has a high reflectance. In this paper, optimizing the number of finger on a $4{\times}4$ solar cell is demonstrated with known theory. We compared the short circuit current density and fill factor to evaluate the power loss from the front metal contact calculation result. By experiment, the short circuit current density($J_{sc}$), taken in each pattern as 37.61, 37.53, and $37.38mA/cm^2$ decreased as the number of fingers increased. The fill factor(FF), measured in each pattern as 0.7745, 0.7782 and 0.7843 increased as number of fingers increased. The results suggested that the efficiency(Eff) was measured in each pattern as 17.51, 17.81, and 17.84 %. Throughout this study, the short-circuit current densities($J_{sc}$) and fill factor(FF) varied according to the number of fingers in the front metal pattern. The effects on the efficiency of the two factors were also investigated.

• 한국재료학회지
• /
• 제25권4호
• /
• pp.196-201
• /
• 2015

This paper presents the impact of partial shading on $CuIn_xGa_{(1-x)}Se_2(CIGS)$ photovoltaic(PV) modules with bypass diodes. When the CIGS PV modules were partially shaded, the modules were under conditions of partial reverse bias. We investigated the characterization of the bypass diode and solar cell properties of the CIGS PV modules when these was partially shaded, comparing the results with those for a crystalline silicon module. In crystalline silicon modules, the bypass diode was operated at a partial shade modules of 1.67 % shading. This protected the crystalline silicon module from hot spot damage. In CIGS thin film modules, on the other hand, the bypass diode was not operated before 20 % shading. This caused damage because of hotspots, which occurred as wormlike defects in the CIGS thin film module. Moreover, the bypass diode adapted to the CIGS thin film module was operated fully at 60% shading, while the CIGS thin film module was not operated under these conditions. It is known that the bypass diode adapted to the CIGS thin film module operated more slowly than that of the crystalline silicon module; this bypass diode also failed to protect the module from damage. This was because of the reverse saturation current of the CIGS thin film, $1.99{\times}10^{-5}A/cm^2$, which was higher than that of crystalline silicon, $8.11{\times}10^{-7}A/cm^2$.

• 한국전기전자재료학회논문지
• /
• 제29권8호
• /
• pp.461-465
• /
• 2016

n-type silicon shows the better tolerance towards metal impurities with a higher minority carrier lifetime compared to p-type silicon substrate. Due to better lifetime stability as compared to p-type during illumination made the photovoltaic community to switch toward n-type wafers for high efficiency silicon solar cells. We fabricated the front electrode of the n-type solar cell with AgAl paste. The electrodes characteristics of the AgAl paste depend on the contact junction depth that is closely related to the firing temperature. Metal contact depth with p+ emitter, with optimized depth is important as it influence the resistance. In this study, we optimize the firing condition for the effective formation of the metal depth by varying the firing condition. The firing was carried out at temperatures below $670^{\circ}C$ with low contact depth and high contact resistance. It was noted that the contact resistance was reduced with the increase of firing temperature. The contact resistance of $5.99m{\Omega}cm^2$ was shown for the optimum firing temperature of $865^{\circ}C$. Over $900^{\circ}C$, contact junction is bonded to the Si through the emitter, resulting the contact resistance to shunt. we obtained photovoltaic parameter such as fill factor of 76.68%, short-circuit current of $40.2mA/cm^2$, open-circuit voltage of 620 mV and convert efficiency of 19.11%.

• 한국전기전자재료학회논문지
• /
• 제26권1호
• /
• pp.73-79
• /
• 2013

Crystalline silicon solar cells with $SiN_x/SiN_x$ and $SiN_x/SiO_x$ double layer anti-reflection coatings(ARC) were studied in this paper. Optimizing passivation effect and optical properties of $SiN_x$ and $SiO_x$ layer deposited by PECVD was performed prior to double layer application. When the refractive index (n) of silicon nitride was varied in range of 1.9~2.3, silicon wafer deposited with silicon nitride layer of 80 nm thickness and n= 2.2 showed the effective lifetime of $1,370{\mu}m$. Silicon nitride with n= 1.9 had the smallest extinction coefficient among these conditions. Silicon oxide layer with 110 nm thickness and n= 1.46 showed the extinction coefficient spectrum near to zero in the 300~1,100 nm region, similar to silicon nitride with n= 1.9. Thus silicon nitride with n= 1.9 and silicon oxide with n= 1.46 would be proper as the upper ARC layer with low extinction coefficient, and silicon nitride with n=2.2 as the lower layer with good passivation effect. As a result, the double layer AR coated silicon wafer showed lower surface reflection and so more light absorption, compared with $SiN_x$ single layer. With the completed solar cell with $SiN_x/SiN_x$ of n= 2.2/1.9 and $SiN_x/SiO_x$ of n= 2.2/1.46, the electrical characteristics was improved as ${\Delta}V_{oc}$= 3.7 mV, ${\Delta}_{sc}=0.11mA/cm^2$ and ${\Delta}V_{oc}$=5.2 mV, ${\Delta}J_{sc}=0.23mA/cm^2$, respectively. It led to the efficiency improvement as 0.1% and 0.23%.

• 융복합기술연구소 논문집
• /
• 제8권1호
• /
• pp.33-39
• /
• 2018

The screen printing method for forming the electrode by applying the existing pressure is difficult to apply to thin wafers, and since expensive Ag paste is used, it is difficult to solve the problem of cost reduction. This can solve both of the problems by forming the front electrode using a plating method applicable to a thin wafer. In this paper, the process conditions of electrode formation are optimized by using LIEP (Light-Induced Electrode Plating). Experiments were conducted by varying the Ni plating bath temperature $40{\sim}70^{\circ}C$, the applied current 5 ~ 15 mA, and the plating process time 5 ~ 20 min. As a result of the experiment, it was confirmed that the optimal condition of the structural characteristics was obtained at the plating bath temperature of $60^{\circ}C$, 15 mA, and the process time of 20 min. The Cu LIEP process conditions, experiments were conducted with Cu plating bath temperature $40{\sim}70^{\circ}C$, applied voltage 5 ~ 15 V, plating process time 2 ~ 15 min. As a result of the experiment, it was confirmed that the optimum conditions were obtained as a result of electrical and structural characteristics at the plating bath temperature of $60^{\circ}C$ and applied current of 15 V and process time of 15 min. In order to form Ni silicide, the firing process time was fixed to 2 min and the temperature was changed to $310^{\circ}C$, $330^{\circ}C$, $350^{\circ}C$, and post contact annealing was performed. As a result, the lowest contact resistance value of $2.76{\Omega}$ was obtained at the firing temperature of $310^{\circ}C$. The contact resistivity of $1.07m{\Omega}cm^2$ can be calculated from the conditionally optimized sample. With the plating method using Ni / Cu, the efficiency of the solar cell can be expected to increase due to the increase of the electric conductivity and the decrease of the resistance component in the production of the solar cell, and the application to the thin wafer can be expected.