• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.193-193
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• 2010

서로 다른 유전 물질을 이용하여 다층구조의 터널장벽을 이용하여 비휘발성 메모리 소자의 동작 특성 및 전하보존 특성을 향상시킬 수 있음이 보고되었다.[1-3] 본 연구에서는 $SiO_2/Si_3N_4/SiO_2$구조의 다층 구조의 터널 장벽을 이용하여 $WSi_2$ 나노 입자 비휘발성 메모리 소자를 제작하였다. P-형 Si 기판에 100 nm 두께의 Poly-Si 박막을 증착시켜 소스, 드레인 및 게이트 영역을 포토 리소그래피를 이용하여 형성하였다. $SiO_2/Si_3N_4/SiO_2$(ONO) 터널장벽은 CVD (chemical vapor deposition) 장치로 각각 2 nm, 2 nm 와 3 nm 두께로 형성하였으며, 그 위에 $WSi_2$ 박막을 3~4 nm 마그내트론 스퍼터링 방법으로 증착하였다. ONO 터널 장벽구조 위에 $WSi_2$나노입자를 형성시키기 위해, $N_2$분위기에서 급속열처리 방법을 이용하여 $900^{\circ}C$에서 1분간 열처리를 하였다. 마지막으로 20 nm 두께의 컨트롤 절연막을 초고진공 스퍼터를 이용하여 증착하고, Al 박막을 200 nm 두께로 증착하였다. 여기서. 제작된 메모리 소자의 게이트 길이와 선폭은 모두 $10\;{\mu}m$ 이다. 비휘발성 메모리 소자의 전기적 특성은 HP 4156A 반도체 파라미터 장비, Agilent 81104 A 80MHz 펄스/패턴 발생기를 이용하였다. 또한 전하 저장 터널링 메커니즘과, 전하누설의 원인을 분석하고 소자의 열적 안정성을 확인하기 위하여 $25^{\circ}C$ 에서 $125^{\circ}C$ 로 온도를 변화시켜 외부로 방출되는 전하의 활성화 에너지를 확인하여 누설근원을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.332-332
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• 2012

프로그래밍 단자와 채널 단자가 게이트 산화 막으로 절연되는 플래시 스위치 및 SRAM 스위치와는 달리 상변화 스위치에서는 채널 단자를 통해 흐르는 전기신호가 프로그래밍 단자를 통해 그대로 누설되는 문제점이 발생한다. 이러한 문제점을 해결하기 위해서 지난 연구에서는 칼코겐화물로 구성되는 다층구조를 제안하고 $Ge_2Sb_2Te_5$의 특성을 보고하였다. 본 연구에서는 스퍼터링 방식을 이용하여 조성비가 다른 GeSbTe 박막을 증착하고 온도변화에 따른 면 저항 및 표면 형상 변화를 관찰한 후 이를 통해 다층구조에 적용하기에 적합한 조성비를 얻고자 하였다. GeSbTe 박막의 조성비에 따라 면 저항 및 표면형상이 크게 변화 하는 것을 확인 하였으며 이러한 결과로부터 프로그래머블 스위치에 적용되는 칼코겐화물 합금의 조성비는 스위치의 성능 좌우하는 중요한 파라미터임을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9B
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• pp.823-833
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• 2003

To satisfy the requirements of the real-time Internet services, queue management and scheduling schemes should be enhanced to accommodate the delay and jitter characteristic of them. Although the existing queue management schemes can address the congestion problems of TCP flows, they have some problems in supporting real-time services. That is, they show performance degradation when burst traffics are continuously going into the system after the queue is occupied at a predefined threshold level. In addition, under the congestion state, they show large jitter, which is not a desirable phenomenon for real-time transmissions. To resolve these problems, we propose a SDRED (State Dependent Random Early Detection) and dynamic scheduling scheme that can improve delay and jitter performances by adjusting RED parameters such as ma $x_{th}$ and $w_{q}$ according to the queue status. The SDRED is designed to adapt to the current traffic situation by adjusting the max,$_{th}$ and $w_{q}$ to four different levels. From the simulation results, we show that the SDRED decreases packet delays in a queue and has more stable jitter characteristics than the existing RED, BLUE, ARED and DSRED schemes.mes.mes.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.4
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• pp.125-136
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• 2011

The vulnerabilities existed in Korean electricity control systems is unexposed because it is being operated in a closed network with superior security. The threat will become greater once the closed network develops into a smart grid environment with superior intelligence. Security will have a greater impact once each household will be connected to the power plant via the smart meter. This research focuses on stable data transfer in harsh external environment and whole-nation coverage network, and suggested standardized and optimized Virtual Private Network (VPN) Gateway architecture to support Power Line Communication (PLC). The functionality and stability of the prototype has been verified with field tests. For implementation of outdoor type VPN device for smart grid, we adopted PLC low voltage remote-meter-net for data communication. Also, IPSec type tunneling and ARIA algorithm based encryption of data collected by PLC low voltage remote meter is transmitted.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of IKEEE
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• v.24 no.2
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• pp.632-637
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• 2020

The non-intrusive load monitoring (NILM) is an important way to cost-effective real-time monitoring the energy consumption and time of use for each appliance in a home or business using aggregated energy from a single recording meter. In this paper, we collect from the smart farm's power consumption data acquisition system to the server via an LTE modem, converted the total power consumption, and the power of individual electric devices into HDF5 format and performed NILM analysis. We perform NILM analysis using open source denoising autoencoder (DAE), long short-term memory (LSTM), gated recurrent unit (GRU), and sequence-to-point (seq2point) learning methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.