• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.5
• /
• pp.992-997
• /
• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.4
• /
• pp.1-6
• /
• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.3
• /
• pp.541-546
• /
• 2008

In this paper, conduction phenomena have been considered for nano structure double gate MOSFET, using the analytical model. The Possion equation is used to analytical model. The conduction mechanisms to have an influence on current conduction are thermionic emission and tunneling current, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. The deviation of current path and the influence of current path on subthreshold swing have been considered according to the dimensional parameters of double gate MOSFET, i.e. gate length, gate oxide thickness, channel thickness. The optimum channel doping concentration is determined as the deviation of conduction path is considered according doping concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.5-8
• /
• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거 하기 위해서, 베이스 부분의 매몰충을 줄여서 npn트랜지스터의 베이스와 에피충과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 소자 시뮬레이션의 자료를 얻기 위하여 수직 npn 트랜지스터와 병합 pnp 트랜지스터의 전류-전압 특성을 분석하여 특성 파라미터를 추출하였다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 형성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.861-864
• /
• 2006

In this paper conduction phenomena have been considered for nano structure double gate MOSFET, using the analytical model. The Possion equation is used to obtain the analytical model. The conduction mechanisms to have an influence on current conduction are thermionic emission and tunneling current, and subthreshold swings of this paper is compared with those of two dimensional simulation to verify this model. The deviation of current path and the influence of current path on subthreshold swing have been considered according to the dimensional parameters of double gate MOSFET, i.e. gate length, gateoxide thickness, channel thickness. The optimum channel doping concentration is determined as the deviation of conduction path is considered according to channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.7
• /
• pp.1617-1622
• /
• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.185-185
• /
• 2013

반도체 트랜지스터의 집적화 기술이 발달하고 소자가 나노미터 크기로 집적화 됨에 따라 문턱 전압의 변동, 높은 누설 전류, 문턱전압 이하에서의 기울기의 열화와 같은 단 채널 효과가 문제되고 있다. 이러한 문제점들은 비 휘발성 플래시 메모리에서 메모리 윈도우의 감소에 따른 retention 특성을 저하시킨다. 이중 게이트 구조의 metal-oxide-semiconductor field-effect-transistors (MOSFETs)은 이러한 단 채널 효과 중에서도 특히 문턱 전압의 변동을 억제하기 위해 제안되었다. 이중 게이트 MOSFETs는 상부 게이트와 하부 게이트 사이의 capacitive coupling을 이용하여 문턱전압의 변동의 제어가 용이하다는 장점을 가진다.기존의 플래시 메모리는 쓰기 및 지우기 (P/E) 동작, 그리고 읽기 동작이 채널 상부의 컨트롤 게이트에 의하여 이루어지며, 메모리 윈도우 및 신뢰성은 플로팅 게이트의 전하량의 변화에 크게 의존한다. 이에 따라 메모리 윈도우의 크기가 결정되고, 높은 P/E 전압이 요구되며, 터널링 산화막에 인가되는 높은 전계에 의하여 retention에서의 메모리 윈도우의 감소와 산화막의 물리적 손상을 초래하기 때문에 신뢰성 및 수명을 열화시키는 원인이 된다. 따라서 본 연구에서는, 상부 게이트 산화막과 하부 게이트 산화막 사이의 capacitive coupling 효과에 의하여 하부 게이트로 읽기 동작을 수행하면 메모리 윈도우를 크게 증폭시킬 수 있고, 이에 따라 동작 전압을 감소시킬 수 있는 이중 게이트 구조의 플래시 메모리를 제작하였다. 그 결과, capacitive coupling 효과에 의하여 크게 증폭된 메모리 윈도우를 얻을 수 있음을 확인하였고, 저전압 구동 및 신뢰성을 향상시킬 수 있음을 확인하였다.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.16 no.3
• /
• pp.15-27
• /
• 2017

In general, increasing train dwell time leads to increasing train service frequency, and it in turn contributes to increasing the congestion level of train and platform. Therefore, the studies on train dwell time have received growing attention in the perspective of scheduling train operation. This study develops a prediction model of train dwell time to enable train operators to mitigate platform congestion by metering passenger inflow at platform gate with respect to platform congestion levels in real-time. To estimate the prediction model, three types of independent variables were applied: number of passengers to get into train, number of passengers to get out of trains, and train weights, which are collectable in real-time. The explanatory power of the estimated model was 0.809, and all of the dependent variables were statistically significant at the 99%. As a result, this model can be available for the basis of on-time train service through platform gate metering, which is a strategy to manage passenger inflow at the platform.

• Journal of Korea Society of Industrial Information Systems
• /
• v.7 no.5
• /
• pp.147-153
• /
• 2002

In this paper, a substrate network model to be used with BSIM3 MOSFET model for submicron MOSFETs in giga hertz frequencies and its direct parameter extraction with physically meaningful values are proposed. The proposed substrate network model includes a conventional resistance and single inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed without any optimization process. The proposed modeling technique has been applied to various-sized MOS transistors. The substrate model has been validated for frequency up to 300Hz.

• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2002.11a
• /
• pp.363-370
• /
• 2002

A substrate network model characterizing substrate effect of submicron MOS transistors for RF operation and its parameter extraction with physically meaningful values are presented. The proposed substrate network model includes a single resistance and inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed with out any optimization. The proposed modeling technique has been applied to various-sized MOS transistors. Excellent agreement the measurement data and the simulation results using extracted substrate network model up to 30GHz.