• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.171-173
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• 2016

일반적으로 대형 버스 및 트럭 등 같은 경우, 부하가 아주 크다. 또한 내리막길이나 장거리 운행 시에 잦은 제동으로 인하여 마찰을 이용한 기존 방식의 브레이크들은 브레이크 파열 및 페이드 현상 때문에 제동 안전성에 문제가 있다. 이러한 제동 부담을 분담하기 위해 현재 보조브레이크(리타더)가 필수적이며, 엔진 계통의 보조브레이크가 아닌 비접촉식 브레이크 같은 친환경 보조브레이크가 요구되고 있다. 그리고 차량 제동시 발생하는 기계에너지를 전기에너지로 회생하여 에너지효율을 향상시키려는 연구가 현재 활발히 진행되고 있다. 본 논문에서는 와전류를 이용한 전자기형 리타더에서 발생되는 전기에너지를 회수하기 위한 전압 제어 방법을 다룰 것이다. 리타더의 제동에너지를 전기에너지로 회생하기 위해 L-C 공진회로로 구성하였다. 리타더를 자여자 유도발전기(Self-Excited Induction Generator)로 모델링 하였고 이를 토대로 시뮬레이션 및 실험을 진행하였다. 자여자 유도발전기의 구동 조건에 대해서 언급하고 이를 파라미터에 따라 3-D map으로 만들었다. 또 회로 중의 FET 게이트에 전압을 인가하는 제어장치의 구동펄스에 따라 바뀌는 공진회로의 전압을 분석하였으며, 이 전압을 제어하기 위하여 PI 제어기를 이용한 알고리즘을 제안하였다. 이 전압을 3상 AC/DC컨버터를 통과한 후 DC/DC컨버터를 통하여 차량 내부의 배터리에 충전되는데 제어를 위해 3상 AC/DC에서의 전압 리플을 MA(Moving Average) 방식의 필터를 사용하여 DC/DC컨버터의 입력에 맞도록 제어하였다. 이와 같이 전자기형 리타더에서 유도되는 전압을 제어기의 제어 펄스에 따라 제어할 수 있으며 Matlab Simulink를 이용하여 리타더의 모델과 그 제어기의 타당성을 보였다. 또 실제 M-G Set 실험을 통하여 그 연관성을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of IKEEE
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• v.23 no.2
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• pp.425-430
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• 2019

This work describes the design and characterization of a X-band power amplifier (PA) monolithic microwave integrated circuit (MMIC) using a $0.25{\mu}m$ gate length gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed X-band power amplifier MMIC has small signal gain of over 22.7 dB and saturated output power of 43.02 dBm (20.04 W) over the entire band of 9 to 10 GHz. Maximum saturated output power is a 43.84 dBm (24.21 W) at 9.5 GHz. Its power added efficiency (PAE) is 41.0~51.24% and the chip dimensions are $3.7mm{\times}2.3mm$, generating the output power density of $2.84W/mm^2$. The developed GaN power amplifier MMIC is expected to be applied in a variety of X-band radar applications.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.439-446
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• 2019

In this paper, we propose a encryption method using C-MLCA and 1D CAT to secure medical image for efficiently. First, we generate a state transition matrix using a Wolfram rule and create a sequence of maximum length. By operating the complemented vector, it converts an existing sequence to a more complex sequence. Then, we multiply the two sequences by rows and columns to generate C-MLCA basis images of the original image size and go through a XOR operation. Finally, we will get the encrypted image to operate the 1D CAT basis function created by setting the gateway values and the image which is calculated by transform coefficients. By comparing the encrypted image with the original image, we evaluate to analyze the histogram and PSNR. Also, by analyzing NPCR and key space, we confirmed that the proposed encryption method has a high level of stability and security.

• Journal of IKEEE
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• v.24 no.4
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• pp.1093-1097
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• 2020

This work describes the design and characterization of a Ku-band monolithic microwave integrated circuit (MMIC) power amplifier (PA) for satellite communication applications. The device technology used relies on 0.25 ㎛ gate length gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT) of wireless information networking (WIN) semiconductor foundry. The developed Ku-band PHEMT MMIC power amplifier has a small-signal gain of 22.2~23.1 dB and saturated output power of 34.8~35.4 dBm over the entire band of 13.75 to 14.5 GHz. Maximum saturated output power is a 35.4 dBm (3.47 W) at 13.75 GHz. Its power added efficiency (PAE) is 30.6~37.83% and the chip dimensions are 4.4 mm×1.9 mm. The developed 3 W PHEMT MMIC power amplifier is expected to be applied in a variety of Ku-band satellite communication applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.77-87
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• 2001

This paper describes a design of cryptographic processor that implements the Rijndael cipher algorithm, the Advanced Encryption Standard algorithm. It can execute both encryption and decryption, and supports only 128-bit block and 128-bit keys. As the processor is implemented only one round, it must iterate 11 times to perform an encryption/decryption. We implemented the ByteSub and InvByteSub transformation using the algorithm for minimizing the increase of area which is caused by different encryption and decryption. It could reduce the memory size by half than implementing, with only ROM. We estimate that the cryptographic processor consists of about 15,000 gates, 32K-bit ROM and 1408-bit RAM, and has a throughput of 1.28 Gbps at 110 MHz clock based on Samsung 0.5um CMOS standard cell library. To our knowledge, this offers more reduced memory size compared to previously reported implementations with the same performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of Sensor Science and Technology
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• v.30 no.6
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.