• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.245-246
• /
• 2008

고밀도 트렌치 공정을 위해 HBr 가스를 주로하고 $CF_4$, $SiF_4$, $NF_3$, He-$O_2$ 등을 첨가 가스로 이용하여 트렌치 공정을 하였다. 트렌치 공정시 첨가가스 비에 따라 트렌치 형상이 다양하게 되었다. 이러한 형상은 트렌치 소자 제조시 트렌치 내부를 채울 경우 여러 가지 어려움이 발생되는데, 특히 트렌치 내부가 잘 채워지지 않고 void가 생길 경우 소자의 신뢰성에 많은 영향을 미칠 수 있다. 본 연구에서는 고밀도 트렌치를 병렬로 형성한 후 형성된 트렌치 내부를 잘 채울수 있는 고밀도 트렌치 공정을 연구하였다. 트렌치 형성시 HBr을 주가스로 하고, $NF_3$, $CF_4$, $SiF_4$ 를 비율을 각각 59:27:7:7로 했을 때 수십만 트렌치 형성 각도가 약 $89^{\circ}$로 매우 좋은 형상을 얻었다.

• Korean Journal of Materials Research
• /
• v.14 no.1
• /
• pp.46-51
• /
• 2004

The annealing of a Cu(4.5at.% Mg)/$SiO_2$/Si structure in ambient $O_2$, at 10 mTorr, and $300-500^{\circ}C$, allows for the outdiffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned, and successfully served as a hard mask, for the subsequent dry etching of the underlying Mg-depleted Cu films using an $O_2$ plasma and hexafluoroacetylacetone [H(hfac)] chemistry. The resultant MgO/Cu structure, with a taper slope of about $30^{\circ}C$ shows the feasibility of the dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.% Mg) gate a-Si:H TFT has a field effect mobility of 0.86 $\textrm{cm}^2$/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films, which eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.

• Korean Journal of Materials Research
• /
• v.14 no.8
• /
• pp.573-578
• /
• 2004

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared $NiCoSi_x$ silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of $NiCoSi_x$ layers. We dry etched the photoresist/SiO/silicide/silicon patterns with $CF_4\;and\;CHF_3$ gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched $0\sim316{\AA}$ during over etch time of 3min, while silicon layers with proposed $NiCoSi_x$ silicide were not etched and showed stable surfaces. Our result implies that new $NiCoSi_x$ silicides may replace the conventional silicides due to contact etch process compatibility.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.11
• /
• pp.902-909
• /
• 1991

A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.375-378
• /
• 2002

We investigated the reduction of etching damage by additive O$_2$ in etching gas and recovery of etching damage by O$_2$ annealing. The PZT thin films were etched using additive Ar or O$_2$ into Cl$_2$/CF$_4$ gas mixing ratio of 8/2. In order to recover ferroelectric properties of PZT thin films after etching, the etched PZT thin films were annealed at 600 C in O$_2$ atmosphere for 10 min. The remanent polarization is decreased seriously and fatigue is accelerated in the PZT sample etched in Ar/(C1$_2$+CF$_4$) plasma, whereas these characteristics are improved in O$_2$/(Cl$_2$/CF$_4$). From x-ray photoelectron spectroscopy (XPS) analysis, the intensities of Pb-O, Zr-O and Ti-O peaks are changed and the etch byproducts such as metal chloride and metal fluoride are reduced by O$_2$ annealing. From electron probe micro analyzer (EPMA) and auger electron spectroscopy(AES), O$_2$ vacancy is observed after etching. In x-ray diffraction (XRD), the structure damage in the additive O$_2$ into C1$_2$/CF$_4$ is reduced and the improvement of ferroelectric behavioral annealed sample is consistent with the increase of the (100) and (200) PZT peaks.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.243-243
• /
• 2010

This paper two different etching, HF : HNO3 :DI and RIE were used for etching in multi-crystalline Silicon(Mc-Si) solar cell fabrication. The wafers etched in RIE texture showed low reflectance compared to the wafers etched in Acid soultion after SiNx deposition. In light current-voltage results, the cells etched in RIE texture exhibited higher short circuit current and open circuit voltage than those of the cells etched in acid solution. We have obtained 15.1% conversion efficiency in large area($156cm^2$) Multi-Si solar cells etched in RIE texture.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.1
• /
• pp.31-43
• /
• 1993

Thermal behavior and $O_{2}$ plasma effects on residue and penetrated impurities formed by reactive ion etching (RIE) in CHF$_{3}$/C$_{2}$F$_{6}$ have been investigated using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) techniques. Decomposition of polymer residue film begins between 200-300.deg. C, and above 400.deg. C carbon compound as graphite mainly forms by in-situ resistive heating. It reveals that thermal decomposition of residue can be completed by rapid thermal anneal above 800.deg. C under nitrogen atmosphere and out-diffusion of penetrated impurities is observed. The residue layer has been removed with $O_{2}$ plasma exposure of etched silicon and its chemical bonding states have been changed into F-O, C-O etc.. And $O_{2}$ plasma exposure results in the decrease of penetrated impurities.

• Proceedings of the KIEE Conference
• /
• 1999.11d
• /
• pp.1137-1139
• /
• 1999

저가의 우수한 성능을 갖는 적외선 영상표시 소자 구현에 적합한 마이크로 볼로미터를 MEMS 기술을 사용하여 제작하였다. 작은 열질량을 갖는 마이크로미터 단위의 열적고립 구조(thermal isolation structure) 제작은 폴리이미드(PI2611)를 희생층으로 사용하여 최종적으로 ashing공정 단계에서 폴리이미드를 제거하여 마이크로 볼로미터 구조를 완성하였다. 이 때의 구조층으로는 PECVD 질화실리콘($SiN_x$) 박막, 감지층으로 산화바나듐($VO_x$) 박막을 사용하였다. 본 연구에서는 폴리이미드 패턴 형성시 건식식각 공정조건 변수에 따라서 패턴의 기울기를 조절하여 폴리이미드 측면에서 발생되는 불 균일한 박막 증착과 패터닝 문제를 개선하였다. 또한 저응력의 질화실리콘 박막을 사용하여 잔류응력에 의한 열적고립 구조의 뒤틀림 현상을 완화하였다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2010.05a
• /
• pp.32.2-32.2
• /
• 2010

본 연구에서는 고출력, 고휘도를 위해서 개발되고 있는 수직형 LED소자의 광출력향상을 위한 나노 패터닝 공정을 진행하였다. 수직형 LED는 기존 측면형 LED에 비해서 열방출 특성이 우수하고 대면적 칩으로 제작이 가능하기 때문에 높은 광출력이 필요한 조명 분야로의 적용이 가능하다. 하지만 수직형 LED 역시 기존 측면형 LED와 마찬가지로 질화갈륨 및 외부 공기와의 계면에서 전반사가 심하기 때문에 광추출효율이 낮은 문제점이 있으며 이를 해결하는 것이 큰 이슈가 되고 있다. 이를 해결하기 위해서 광결정 패턴을 LED 소자에 형성하여 광추출효율을 향상시키려는 연구가 활발히 진행되고 있으나 아직까지 수직형 LED 웨이퍼 전면적에 균일한 패턴을 형성할 수 있는 기술 개발이 미진한 상황이다. 본 연구에서는 유연 고분자 몰드를 이용한 대면적 나노 임프린팅 및 나노 프린팅 기술을 통해서 2 inch 수직형 LED 웨이퍼 전면적에 균일한 패턴을 전사하는 공정을 진행하였다. 구체적으로는 나노임프린트 및 건식식각 공정을 통해서 수직형 LED의 n형 질화갈륨 층에 높은 가로세로비의 광결정 패턴을 형성하였으며 이를 통해서 약 40% 정도의 광출력이 향상되었다. 또한 고 굴절률의 산화아연 나노 패턴 형성공정을 대면적 LED 기판에 시도하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.8
• /
• pp.455-460
• /
• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).