• Journal for History of Mathematics
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• v.22 no.4
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• pp.115-128
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• 2009

In this paper, we modify the axiom of infinity of von Neumann's axioms modified by Pinter([5]), and then discuss an existence of an unknowable class in the system and a relationship between the unknowable class and the axiom of choice.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• The Korean Journal of Applied Statistics
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• v.10 no.1
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• pp.105-119
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• 1997

Barnwal and Paul(1988) derived the likelihood ratio statistic and $C(\alpha)$ statistic for testing the equality of the means of several groups of count data in the presence of a common dispersion parameter. These tests are generalized to be applicable without the restriction of a common dispersion parameter. And the assumed model of data is also extended from negative binomial to double exponential Poisson model. Monte Carlo simulations show the superiority of $C(\alpha)$ statistic based on the double exponential Poisson family which has a very simple form and requires estimates of the parameters only under the null hypothesis.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.13-19
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• 1998

The Median of a set of number is a number which partitions the given set. The specified numbers of a set partitions in one subset and in another subset. In Image Processing, The Sorting method of numbers of one subset equal to the previous Median Filtering. but The Sorting method of numbers of another subset not equal to in the other. In this paper, a fast two-dimentional Median Filtering Algorithm is proposed. The Algorithm designed in such a during the partitioning of the previous window are used. Test results obtained by running the Algorithm on IBM PC(586) are presented and its filtering. It is shown that the proposed Algorithm's processing time is faster and independent of the number of bits used to represent the data values.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.2
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• pp.9-14
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• 2022

This paper presents a subset sum problem (SSP) algorithm which takes the time complexity of O(nlogn). The SSP can be classified into either super-increasing sequence or random sequence depending on the element of Set S. Additive algorithm that runs in O(nlogn) has already been proposed to and utilized for the super-increasing sequence SSP, but exhaustive Brute-Force method with time complexity of O(n2ⁿ) remains as the only viable algorithm for the random sequence SSP, which is thus considered NP-complete. The proposed subtractive algorithm basically selects a subset S comprised of values lower than target value t, then sets the subset sum less the target value as the Residual r, only to remove from S the maximum value among those lower than t. When tested on various super-increasing and random sequence SSPs, the algorithm has obtained optimal solutions running less than the cardinality of S. It can therefore be used as a general algorithm for the SSP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.10
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• pp.1886-1891
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• 2017

Denoising which is one of major research topics in the image processing deals with recovering the noisy images. Natural images are well known not only for their local but also nonlocal similarity. Patterns of unique edges and texture which are crucial for understanding the image are repeated over the nonlocal region. In this paper, a nonlocal similarity based denoising algorithm is proposed. First for every blocks of the noisy image, nonlocal similar blocks are gathered to construct a overcomplete data set which are inherently sparse in the transform domain due to the characteristics of the images. Then, the sparse transform coefficients are filtered to suppress the non-sparse additive noise. Finally, the image is recovered by aggregating the overcomplete estimates of each pixel. Performance experiments with several images show that the proposed algorithm outperforms the conventional methods in removing the additive Gaussian noise effectively while preserving the image details.

• Communications of Mathematical Education
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• v.22 no.4
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• pp.471-487
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• 2008

Inventive mathematical thinking, original mathematical problem solving ability, mathematical invention and so on are core concepts, which must be emphasized in all branches of mathematical education. In particular, Polya(1981) insisted that inventive thinking must be emphasized in a suitable level of university mathematical courses. In this paper, the author considered two cases of inventive problem solving ability shown by his many students via real analysis courses. The first case is about the proof of the problem "what is the derived set of the integers Z?" Nearly all books on mathematical analysis sent the question without the proof but some books said that the answer is "empty". Only one book written by Noh, Y. S.(2006) showed the proof by using the definition of accumulation points. But the proof process has some mistakes. But our student Kang, D. S. showed the perfect proof by using The Completeness Axiom, which is very useful in mathematical analysis. The second case is to show the infinite countability of NxN, which is shown by informal proof in many mathematical analysis books with formal proofs. Some students who argued the informal proof as an unreasonable proof were asked to join with us in finding the one-to-one correspondences between NxN and N. Many students worked hard and find two singled-valued mappings and one set-valued mapping covering eight diagrams in the paper. The problems are not easy and the proofs are a little complicated. All the proofs shown in this paper are original and right, so the proofs are deserving of inventive mathematical thoughts, original mathematical problem solving abilities and mathematical inventions. From the inventive proofs of his students, the author confirmed that any students can develope their mathematical abilities by their professors' encouragements.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.