• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.575-582
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• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• Journal of Bio-Environment Control
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• v.3 no.1
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• pp.42-51
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• 1994

Visual features of a mushromm(Lentinus Edodes L.) are critical in sorting and grading as most agricultural products are. Because of its complex and various visual features, grading and sorting of mushrooms have been done manually by the human expert. Though actions involved in human grading look simple, it decision making underneath the simple action comes from the result of the complex neural processing of visual image. Recently, an artificial neural network has drawn a great attention because of its functional capability as a partial substitute of the human brain. Since most agricultural products are not uniquely defined in its physical properties and do not have a well defined job structure, the neuro -net based computer visual information processing is the promising approach toward the automation in the agricultural field. In this paper, first, the neuro - net based classification of simple geometric primitives were done and the generalization property of the network was tested for degraded primitives. And then the neuro-net based grading system was developed for a mushroom. A computer vision system was utilized for extracting and quantifying the qualitative visual features of sampled mushrooms. The extracted visual features of sampled mushrooms and their corresponding grades were used as input/output pairs for training the neural network. The grading performance of the trained network for the mushrooms graded previously by the expert were also presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.179-184
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• 2019

In many countries, such as developing countries where electricity is scarce, small wind turbines in the form of Off Grid are an effective solution to solve power supply problems. In some countries, the expansion of power systems and the decline of electricity-intensive areas have led to the use of small wind power in urban road lighting, mobile communications base stations, aquaculture and seawater desalination. With this change, the size of the small wind power industry is expected to have greater potential than large-scale wind power. In the case of small wind power generators, the generator is controlled at a variable speed, and the voltage and current generated by the generator have many harmonic components. To solve this problem, the AC to DC converter to be studied in this paper is a three-phase step-up type converter with a single switch. The inductor current is controlled in discontinuous mode, and has a characteristic of having a unit power factor by eliminating the harmonic of the input current. The proposed converter is composed of LCL filter and three phase rectification boost converter at the input stage and a single phase full bridge for grid connection. It is a control system with energy storage system(ESS) that the system stabilization can be pursued against the electric power.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.17-24
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• 2014

In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.35-43
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• 2008

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of KIISE
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• v.43 no.12
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• pp.1365-1375
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• 2016

One of the most important capabilities for autonomous service robots working in living environments is to recognize and understand the correct context in dynamically changing environment. To generate high-level context knowledge for decision-making from multiple sensory data streams, many technical problems such as multi-modal sensory data fusion, uncertainty handling, symbolic knowledge grounding, time dependency, dynamics, and time-constrained spatio-temporal reasoning should be solved. Considering these problems, this paper proposes an effective dynamic context management and spatio-temporal reasoning method for intelligent service robots. In order to guarantee efficient context management and reasoning, our algorithm was designed to generate low-level context knowledge reactively for every input sensory or perception data, while postponing high-level context knowledge generation until it was demanded by the decision-making module. When high-level context knowledge is demanded, it is derived through backward spatio-temporal reasoning. In experiments with Turtlebot using Kinect visual sensor, the dynamic context management and spatio-temporal reasoning system based on the proposed method showed high performance.