• 제목/요약/키워드: (Bi,La)${Ti_3}{O_{12}}$

검색결과 84건 처리시간 0.031초

FRAM 응용을 위한 건조온도에 따른 BLT 박막의 강유전 특성 (Ferroelectric Properties of Bi3.25La0.75Ti3O12 Thin Films with Various Drying Temperature for FRAM Applications)

  • 김경태;김동표;김창일;김태형;강동희;심일운
    • 한국전기전자재료학회논문지
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    • 제16권4호
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    • pp.265-271
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    • 2003
  • Ferroelectric lanthanum-substituted Bi$_4$Ti$_3$O$_{12}$(BLT) thin films were fabricated by spin-coating onto a Pt/Ti/SiO$_2$/Si substrate by metalorganic decomposition technique. The grain size in BLT thin films were prepared with controlled by various drying process. The effect of grain size on the crystallization and ferroelectric properties were investigated by x-ray diffraction and field emission scanning electron microscope. The dependence of crystallization and electrical properties are related to the grain size in BLT thin films with different drying temperature. The remanent polarization of BLT thin film increases with the increasing grain size. The value of 2P$_{r}$ and E$_{c}$ of BLT thin film dried at 45$0^{\circ}C$ were 25.9 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm, respectively. The BLT thin film with larger grain size has better fatigue properties. The fatigue properties revealed that small grained film showed more degradation of switching charge than large grained films.lms.s.

$(Bi,La)Ti_3O_{12}$ 강유전체 박막 게이트를 갖는 전계효과 트랜지스터 소자의 제작 (Preparation of Field Effect Transistor with $(Bi,La)Ti_3O_{12}$ Ferroelectric Thin Film Gate)

  • 서강모;박지호;공수철;장호정;장영철;심선일;김용태
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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    • pp.221-225
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    • 2003
  • The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

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RF magnetron sputtering법에 의한 BLT 박막의 후열처리 온도에 관한 영향 (The effect of post-annealing temperature on $Bi_{3.25}La_{0.75}Ti_3O_{12}$ thin films deposited by RF magnetron sputtering)

  • 이기세;이규일;박영;강현일;송준태
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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    • pp.624-627
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    • 2003
  • The BLT thin-films were one of the promising ferroelectric materials with a good leakage current and degradation behavior on Pt electrode. The BLT target was sintered at $1100^{\circ}C$ for 4 hours at the air ambient. $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin-film deposited on $Pt/Ti/SIO_2/Si$ wafer by rf magnetron sputtering method. At annealed $700^{\circ}C$, (117) and (006) peaks appeared the high intensity. The hysteresis loop of the BLT thin films showed that the remanent polarization ($2Pr=Pr^+-Pr^-$) was $16uC/cm^2$ and leakage current density was $1.8{\times}10^{-9}A/cm^2$ at 50 kV/cm with coersive electric field when BLT thin-films were annealed at $700^{\circ}C$. Also, the thin film showed fatigue property at least up to $10^{10}$ switching bipolar pulse cycles under 7 V. Therefore, we induce access to optimum fabrication condition of memory device application by rf-magnetron sputtering method in this report.

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고밀도 강유전체 메모리 소자 제작 시 발생하는 $(Bi,La)_4Ti_3O_{12}$ 커패시터의 불량 분석 (Failure Analysis of Ferroelectric $(Bi,La)_4Ti_3O_{12}$ Capacitor in Fabricating High Density FeRAM Device)

  • 김영민;장건익;김남경;염승진;홍석경;권순용
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.257-257
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    • 2007
  • 고밀도 FeRAM (Ferroe!ectric Random Access Memory) 소자를 개발하기 위해서는 강유전체 물질을 이용한 안정적인 스텍형의 커패시터 개발이 필수적이다. 특히 $(Bi,La)_4Ti_3O_{12}$ (BLT) 강유전체 물질을 이용하는 경우에는 낮은 열처리 온도에서도 균질하고 높은 값의 잔류 분극 값을 확보하는 것이 가장 중요한 과제 중의 하나이다. 불행히도, BLT 물질은 a-축으로는 약 $50\;{\mu}C/cm^2$ 정도의 높은 잔류 분극 값을 갖지만, c-축 방향으로는 $4\;{\mu}C/cm^2$ 정도의 낮은 잔류 분극 값을 나타내는 동의 강한 비등방성 특성을 보인다. 따라서 BLT 박막에서 각각 입자들의 크기 및 결정 방향성을 세밀하게 제어하는 것은 무엇보다 중요하다. 본 연구에서는 16 Mb의 1T/1C (1-transistor/1-capacitor) 형의 FeRAM 소자를 BLT 박막을 적용하여 제작하였다. 솔-젤 (sol-gel) 용액을 이용하여 스핀코팅법으로 BLT 박막을 증착하고, 후속 열처리 공정을 RTP (rapid thermal process) 공정을 이용하여 수행하였다. 커패시터의 하부 전극 및 상부 전극은 각각 Pt/IrOx/lr 및 Pt을 적용하였다. 반응성 이온 에칭 (RIE: reactive ion etching) 공정을 이용하여 커패시터를 형성시킨 후, 32k-array (unit capacitor: $0.68\;{\mu}m$) 패턴에서 측정한 스위칭 분극 (dP=P*-P^) 값은 약 $16\;{\mu}C/cm^2$ 정도이고, 웨이퍼 내에서의 균일도도 2.8% 정도로 매우 우수한 특성을 보였다. 그러나 단위 셀들의 특성을 평가하기 위하여 bit-line의 전압을 측정한 결과, 약 10% 정도의 커패시터에서 불량이 발생하였다. 그리고 이러한 불량 젤들은 매우 불규칙적으로 분포함을 확인할 수 있었다. 이러한 불량 원인을 파악하기 위하여 양호한 젤과 불량이 발생한 셀에서의 BLT 박막의 미세구조를 분석하였다. 양호한 셀의 BLT 박막 입자들은 불량한 셀에 비하여 작고 비교적 균일한 크기를 갖고 있었다. 이에 비하여 불량한 셀에서의 BLT 박막에는 과대 성장한 입자들이 존재하고 이에 따라서 입자 크기가 매우 불균질한 것으로 확인되었다. 또 이러한 과대 성장한 입자들은 거의 모두 c-축 배향성을 나타내었다. 이상의 실험 결과들로부터, BLT 박막을 이용하여 제작한 FeRAM 소자에서 발생하는 불규칙한 셀 불량의 주된 원인은 c-축 배향성을 갖는 과대 성장한 입자의 생성임을 알 수 있었다. 즉 BLT 박막을 이용하여 FeRAM 소자를 제작하는 경우, 균일한 크기의 입자 및 c-축 배향성의 입자 억제가 매우 중요한 기술적 요소임을 알 수 있었다.

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Current Status and Prospects of FET-type Ferroelectric Memories

  • Ishiwara, Hiroshi
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제1권1호
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    • pp.1-14
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    • 2001
  • Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

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Effects of High-Energy Ball Milling and Sintering Time on the Electric-Field-Induced Strain Properties of Lead-Free BNT-Based Ceramic Composites

  • Nga-Linh Vu;Nga-Linh Vu;Dae-Jun Heo;Thi Hinh Dinh;Chang Won Ahn;Chang Won Ahn;Hyoung-Su Han;Jae-Shin Lee
    • 한국전기전자재료학회논문지
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    • 제36권5호
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    • pp.505-512
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    • 2023
  • This study investigated crystal structures, microstructures, and electric-field-induced strain (EFIS) properties of Bi-based lead-free ferroelectric/relaxor composites. Bi1/2Na0.82K0.18)1/2TiO3 (BNKT) as a ferroelectric material and 0.78Bi1/2(Na0.78K0.22)1/2TiO3-0.02LaFeO3 (BNKT2LF) as a relaxor material were synthesized using a conventional solid-state reaction method, and the resulting BNKT2LF powders were subjected to high-energy ball milling (HEBM) after calcination. As a result, HEBM proved a larger average grain size of sintered samples compared to conventional ball milling (CBM). In addition, the increased sintering time led to grain growth. Furthermore, HEBM treatment and sintering time demonstrated a significant effect on EFIS of BNKT/BNKT2LF composites. At 6 kV/mm, 0.35% of the maximum strain (Smax) was observed in the HEBM sample sintered for 12 h. The unipolar strain curves of CBM samples were almost linear, indicating almost no phase transitions, while HEBM samples displayed phase transitions at 5~6 kV/mm for all sintering time levels, showing the highest Smax/Emax value of 700 pm/V. These results indicated that HEBM treatment with a long sintering time might significantly enhance the electromechanical strain properties of BNT-based ceramics.

BLT박막의 화학적기계적연마 공정시 패턴 크기에 따른 공정 특성 (Process Characteristics by Pattern Size in CMP Process of BLT Films)

  • 신상헌;이우선
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.107-108
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    • 2006
  • In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

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Effects of lanthanum doping on ferroelectric properties of direct-patternable $Bi_{4-x}La_xTi_3O_{12}$ films prepared by photochemical metal-organic deposition

  • Park, Hyeong-Ho;Kim, Hyun-Cheol;Park, Hyung-Ho;Kim, Tae-Song
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.287-287
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    • 2007
  • The ferroelectric and electric properties of UV-irradiated bismuth lanthanum titanate (BLT) films prepared using photosensitive starting precursors were characterized. The effects of lanthanum doping on ferroelectric and electric properties were investigated by polarization-electric field hysteresis loops and leakage current-voltage measurements. X-ray diffractometer and ellipsometry were served to provide the information about the crystalline structure and thickness of the films after annealing. The images of the surface microstructure and direct-patterned BLT films were observed by using scanning electron microscopy. The effects of lanthanum doping on the electric properties of direct-pattern able BLT films and their direct-patterning were studied.

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ONO 버퍼층을 이용한 Metal/Ferroelectrics/Insulator/Semiconductor 구조의 제작 및 특성 (Fabrication and Properties of Metal/Ferroelectrics/Insulator/Semiconductor Structures with ONO buffer layer)

  • 이남열;윤성민;유인규;류상욱;조성목;신웅철;최규정;유병곤;구진근
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.305-309
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    • 2002
  • We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

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