• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.96.2-96.2
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• 2010

The surface morphology and structural properties of polycrystalline silicon (poly-Si) films made in-situ aluminum induced crystallization at various substrate temperature (300~600) was investigated. Silicon films were deposited by hot-wire chemical vapor deposition (HWCVD), as the catalytic or pyrolytic decomposition of precursor gases SiH4 occurs only on the surface of the heated wire. Aluminum films were deposited by DC magnetron sputtering at room temperature. continuous poly-Si films were achieved at low temperature. from cross-section TEM analyses, It was confirmed that poly-Si above $450^{\circ}C$ was successfully grown on and poly-Si films had (111) preferred orientation. As substrate temperature increases, Si(111)/Si(220) ratio was decreased. The electrical properties of poly-Si film were investigated by Hall effect measurement. Poly-Si film was p-type by Al and resistivity and hall effect mobility was affected by substrate temperature.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.245-247
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• 2002

The paper represents the effects of the drive-in process parameters on the residual stress profile of the p+ silicon film. For the quantitative determination of the residual stress profiles, the test samples are doped via the fixed boron diffusion process and four types of the thermal oxidation processes and consecutively etched by the improved process. The residual stress measurement structures with the different thickness are simultaneously fabricated on the same silicon wafer. Since the residual stress profile is not uniform along the direction normal to the surface, the residual stress is assumed to be a polynomial function of the depth. All of the coefficients of the polynomial are determined from the deflections of cantilevers and the displacement of a rotating beam structure. As the drive-in temperature or the drive-in time increases, the boron concentration decreases and the magnitude of the average residual tensile stress decreases. Also, near the surface of the p+ film the residual tensile stress is transformed into the residual compressive stress and its magnitude increases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• New & Renewable Energy
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• v.2 no.3
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• pp.31-36
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• 2006

Superstrate pin amorphous silicon thin-film(a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides(TCO) in order to see the effect of TCO/p-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage VOC than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer(${\mu}c-Si:H$) between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{OC}$ of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{OC}$ of 994mV while keeping fill factor(72.7%) and short circuit current density $J_{SC}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{OC}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.158-161
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• 2006

Superstrate pin amorphous silicon thin-film (a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides (TCO) In order to see the effect of TCO/P-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage $V_{oc}$ than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer $({\mu}c-Si:H)$ between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{oc}$, of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{oc}$, of 994mv while keeping fill factor (72.7%) and short circuit current density $J_{sc}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{oc}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.39-43
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• 2017

It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.257.2-257.2
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• 2015

In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.192-195
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• 2012

We reported diborane ($B_2H_6$) doped wide bandgap hydrogenated amorphous silicon oxide (p-type a-SiOx:H) films prepared by using silane ($SiH_4$) hydrogen ($H_2$) and nitrous oxide ($N_2O$) in a radio frequency (RF) plasma enhanced chemical vapor deposition (PECVD) system. We improved the $E_{opt}$ and conductivity of p-type a-SiOx:H films with various $N_2O$ and $B_2H_6$ ratios and applied those films in regards to the a-Si thin film solar cells. For the single layer p-type a-SiOx:H films, we achieved an optical band gap energy ($E_{opt}$) of 1.91 and 1.99 eV, electrical conductivity of approximately $10^{-7}$ S/cm and activation energy ($E_a$) of 0.57 to 0.52 eV with various $N_2O$ and $B_2H_6$ ratios. We applied those films for the a-Si thin film solar cell and the current-voltage characteristics are as given as: $V_{oc}$ = 853 and 842 mV, $J_{sc}$ = 13.87 and 15.13 $mA/cm^2$. FF = 0.645 and 0.656 and ${\eta}$ = 7.54 and 8.36% with $B_2H_6$ ratios of 0.5 and 1% respectively.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Korean Chemical Engineering Research
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• v.49 no.3
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• pp.338-341
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• 2011

Thin silicon ribbon was used for fabricating flexible silicon p-i-n junction devices, consisting of 100${\times}$100 arrays of pixels in 1 inch on the diagonal. Those passive matrix devices exhibited the rectification ratio $>10^{4}$ owing to smaller cross-talking current than that of p-n junction devices. P-i-n devices fabricated on silica/silicon substrates are easily detached by treatment with hydrofluoric acid and are subsequently transferred onto both PDMS and flexible PET film.