• 센서학회지
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• 제20권4호
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• 한국광학회지
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• 제12권4호
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• pp.312-319
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• 2001

본 연구에서는 기존의 RWG LD(Ridge waveguide laser diode)보다 Ridge 폭의 제어가 쉽고 Planar화에 유리하며 측방향의 굴절률차를 성장층의 두께로 조절이 가능한 Buried RWG LD를 제안하였다. 이론해석의 결과로부터 효율적으로 동작하는 MQW B-RWG(Multi-quantum well buried ridge waveguide)LD를 제작하기 위해서는 제작하고자 하는 Ridge 폭에 따라 측장향 유효굴절률차 $\Delta_{nL}$ 의 임계값보다 약간 크게 되도록 유효굴절률 조절을 위한 $d_2(\lambda_g=1.25{\mu}m, InGaAsP layer) 층과 P-InP cald 층인 $d_3$층의 두께를 제어해야 하며 임계전류값이 최소로 되면서 측방향에서 단일모드로 동작하도록 Ridge 폭을 설계해야 한다. 그리고 측방향 유효굴절률차를 적절히 조절한다면 $6~9{\mu}m$의 Ridgechr을 가지면서 단일모드로 동작하는 LD제작이 가능함을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1270-1273
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• 1997

We have investigated the latchup characteristics of BL/BILLI retrograde twin well CMOS that has the high energy ion implanted buried layer to intend for more improvement of latchup compare to conventional retrograde well and BILLI structures. We explored the dependence of various latchup characteristics such as n+ trigger latchup and p+ trigger latchup on the buried layer implant doses. We show various DC latchup characteristics that allow us to evaluate each technology and suggest guidelines for the reduction of latchup susceptibility.

• 대한금속재료학회지
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• 제46권1호
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 춘계종합학술대회
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Advances in nano research
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• 제3권1호
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.251-254
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• 2001

This paper describes an efficiency improvement of buried contact solar cell (BSCS) with a structure of MgF$_2$/CeO$_2$/Ag/Cu/Ni grid/n$^{+}$ emitter/p-type Si base/p$^{+}$/Al. Theoretical and experimental investigations were performed on a double layer antireflection (DLAR) coating of MgF$_2$/CeO$_2$. We investigated CeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. An optimized DLAR coating shewed a reflectance as low as 2.04 % in the wavelengths ranged from 0.4 ${\mu}{\textrm}{m}$ to 1.1 ${\mu}{\textrm}{m}$. BCSC cell efficiency was improved from 16.2 % without any AR coating to 19.9 % by employing DLAR coatings. Further details on MgF$_2$/CeO$_2$ DLAR coatings on the BCSC cells are presented in this paper.per.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• 한국광학회지
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• 제10권6호
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• pp.518-523
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• 1999

본 연구에서는 meltback 방법으로 mesa 모양을 형성하기 위하여 여러 가지 농도의 용액으로 meltback을 하였으며 InP 기판위에 InGaAsP 활성층과 InP cap층을 가지는 웨이퍼에 mesa 모양을 형성하기 위해서는 성장온도에서 성장용액의 80%인 InGaAsP(1.55$\mu$m)용액이 가장 적합한 것으로 확인되었다. meltback 방법만으로 PBH-LD(planar buried heterosturcture laser diode)를 제작하기 위한 완전한 mesa를 형성하기는 어려우며, 따라서 본 연구에서는 화학에칭에 이어 Meltback 방법을 이용하여 mesa 모양을 형성하고 연속하여 전류 차단층을 형성시킨 PBH-LD(planar buried heterosturcture laser diode)를 제작하였다. 이렇게 제작된 MQW-PBH-LD의 전기 광학적 특성은 공진기 길이가 $300{\mu}m$일 때 임계전류는 10mA, 내부양자효율은 82%, 내부손실은 $9.2cm^{-1}$, 특성온도는 $25~45^{\circ}C$ 사이에서는 65K, $45~65^{\circ}C$사이에서는 42K이었다.