• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• Journal of Information Display
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• v.12 no.4
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• pp.209-212
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• 2011

The threshold voltage shift (${\Delta}V_{th}$) under positive-voltage bias stress (PBS) of InGaZnO (IGZO) thin-film transistors (TFTs) annealed at different temperatures in air was investigated. The dramatic degradation of the electrical performance was observed at the sample that was annealed at $700^{\circ}C$. The degradation of the saturation mobility (${\mu}_{sat}$) resulted from the diffusion of indium atoms into the interface of the IGZO/gate insulator after crystallization, and the degradation of the subthreshold slope (S-factor) was due to the increase in the interfacial and bulk trap density. In spite of the degradation of the electrical performance of the sample that was annealed at $700^{\circ}C$, it showed a smaller ${\Delta}V_{th}$ under PBS conditions for $10^4$ s than the samples that were annealed at $500^{\circ}C$, which is attributed to the nanocrystal-embedded structure. The sample that was annealed at $600^{\circ}C$ showed the best performance and the smallest ${\Delta}V_{th}$ among the fabricated samples with a ${\mu}_{sat}$ of $9.38cm^2/V$ s, an S-factor of 0.46V/decade, and a ${\Delta}V_{th}$ of 0.009V, which is due to the passivation of the defects by high thermal annealing without structural change.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.267.1-267.1
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• 2016

본 연구에서는 nematic 액정의 종류 중 하나인 5CB (4-Cyano-4'-pentylbiphenyl) 물질을 박막 트랜지스터 (TFT)의 passivation 층으로 사용했을 때 그 전기적 특성향상을 확인하였다. RF-magnetron sputtering법으로 증착된 비정질 InGaZnO 박막을 활성층으로 사용한 TFT를 제작하여 그 활성층 위에 drop형식으로 passivation 하였다. 그 결과, drain current (I_DS)가 약 10배 정도 증가하고, linear region(V_D=0.5V)에서 mobility와 subthreshold slope(SS)이 각각 6.7에서 12.2, 0.3에서 0.2로 향상되는 것이 보였다. 이것은 gate bias가 인가되었을 때 freedericksz 전이를 통한 액정의 배향과 이때 형성된 dipole 형성에 의한 것으로 보이며, 이러한 LC의 배향은 편광현미경을 통하여 표면과 수직으로 배향한다는 사실을 확인 할 수 있었고 이 LC-passivation된 a-IGZO TFT의 전기적 특성의 향상에 대한 mechanism을 제시하였다. 그리고 배향한 LC가 가지는 dipole에 의해 bias stress 상황에서 독특한 electron trapping과 recovery의 증폭효과가 나타났다. V_G=+20V의 positive gate bias stress를 1000s동안 가했을 때, passivation되지 않은 a-IGZO TFT의 경우 +4V의 threshold voltage shift(${\Delta}V$_TH)가 발생되었고, 바로 -20V의 negative gate bias를 30s간 가해주었을 때 -2.5V의 ${\Delta}V$_TH가 발생하였다. 반면 LC-passivation된 a-IGZO TFT의 경우 각각 +5V와 -4V의 ${\Delta}V$_TH로 더 큰 변화를 가져왔다. 이러한 LC에 의한 electron trapping/recovery 증폭효과에 대한 model을 제시하였다.

• BMB Reports
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• v.29 no.5
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• pp.393-397
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• 1996

Sprague-Dawley male rats (150 g) were chronically treated with 5 v/v % ethanol admixed with nutritionally complete liquid diet and fed ad libitum for 3 weeks. Controls were pair fed with the isocaloric sucrose liquid diet. One half of each group was exposed to cold stress at $4^{\circ}C$ either for 24 h (for determination of mRNA by in situ hybridization) or for 48 h (for determination of enzyme activity). Chronic ethanol treatment (ethanol) did not affect tyrosine hydroxylase (TH) mRNA level in locus coeruleus (LC) of brain and adrenal medulla (AM) compared to controls. Cold stress showed strong increase of TH mRNA level in LC and AM compared to controls. Pretreated ethanol reduced the increased TH mRNA level by cold stress in LC and AM. Ethanol did not affect TH activity in LC and adrenal glands (adrenals). Cold stress increased TH activity in LC but not in adrenals. Pretreated ethanol did not reduce the increased TH activity by cold stress in LC but this result was not shown in adrenals. It is suggested that ethanol does not affect the message level and enzyme protein level for TH in LC and AM in normal rat. It is also hypothesized that pretreated ethanol reduces the magnitude of acute cold stress response, that is induction of TH mRNA in LC and AM, and does not reduce the increased TH enzyme protein that is also acute cold stress response in LC.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1238_1239
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• 2009

본 논문에서는 ELA poly-Si TFT보다 뛰어난 균일도를 갖고, a-Si:H TFT보다 전기적 안정도가 우수한 PMOS SPC-Si TFT의 특성을 연구하였다. SPC-Si의 계면 특성을 향상 시키기 위해 $SiO_2$ 게이트 절연막을 증착하기 전에 Solid Phase Crystalline 실리콘(SPC-Si) 채널 영역에 다양한 H2 플라즈마 처리를 해주었다. PECVD를 이용하여 100W에서 H2 플라즈마 처리를 5분 해주었을 때 SPC-Si TFT의 전기적 특성이 향상되는 것을 볼 수 있는데, $V_{TH}$가 약 -3.91V, field effect mobility가 $22.68cm^2$/Vs, 그리고 Subthreshold swing이 0.64 정도를 보였다. 또한 소자에 Hot carrier stress($V_{GS}$=14.91V, $V_{DS}$=-15V, for 2,000sec)를 주었을 때도 전기적 특성이 변하지 않았으며, 일정한 bias stress($V_{GS}$=-15V, $V_{DS}$=-10V, for 2,000sec)를 가하였을 때도 $V_{TH}$가 증가하지 않았다. 이러한 결과를 통해 SPC-Si가 poly-Si TFT보다 더욱 안정함을 알 수 있었다.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.813-818
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• 1996

Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$ device shows the memory switching characteristics under d.c. bias. In bulk material, a-As$_{10}$Ge$_{15}$ Te$_{75}$ switching threshold voltage (V$_{th}$) is very high (above 100 volts), but in the case of thin film, V$_{th}$ decreases to a few or ten a few volts. The characteristics of V$_{th}$ depends on the physical dimensions such as the thickness of thin film and the separation between d.c. electrodes, and the annealing conditions. The switching threshold voltage decreases exponentially with increasing annealing temperature and annealing time, but increases linearly with the thickness of thin film and exponentially with increasing the separation between d.c. electrodes. The desirable low switching threshold voltage, therefore, can be obtained by the stabilization through annealing and changing physical dimensions.imensions.sions.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.642-645
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• 2003

We proposed new current source and mirror circuits insensitive to $V_{th}$ variation of poly-Si TFTs. The proposed circuits have been verified by SPICE simulation using poly-Si TFT model. The error currents of the proposed current source and current mirror circuits caused by $V_{th}$ variation reduced less than 6.6% and 4.5% of that of conventional ones, respectively.

• Journal of the Korean Vacuum Society
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• v.12 no.S1
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• pp.33-35
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• 2003

The electrooptic properties of the reflected light in a reflective mode, $45^{\circ}C$twisted nematic liquid crystal (TNLC) cell were investigated in the voltage regions near and away from the Freedericksz transition threshold. The measured reflectivity away from the threshold voltage ($V_th$) could not be described by the model which assurnes a constant tilt angle as well as a linearized distribution of twist angle across the cell, although the data are well fitted near $V_th$. We found that in the voltage region away from $V_th$, the model considering the distributions of the tilt angle and the twist angle should be applied for the calculation of the reflectivity. The director-axis distributions were obtained from the numerical integration of the Euler-Lagrange equation.

• Journal of Sensor Science and Technology
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• v.25 no.6
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• pp.388-393
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• 2016

MPEG-V(ISO/IEC 23005) standardizes normative sensory effects metadata and sensory devices command for adapting the sensory effects between the virtual world and the real world. MPEG-V(Virtual) standardization has been carried out by 3DG(Dimensional Graphics) ad-hoc group inside MPEG Working Group(ISO IEC JTC1/SC29/WG11). For the scent effect, one of the sensory effects within MPEG-V, we proposed an olfactory interaction model including electronic nose and scent display to the ad-hoc group. Recently, we proposed types and elements related to the electronic nose as a sensor defined in MPEG-V standard for olfactory interaction. At the 114th MPEG meeting, the types and elements were consequently reflected on MPEG-V CD(Committee Draft) 4th edition. In this paper, we implement an electronic nose system applicable to MPEG-V standard by using MPEG-V schema, encoder, and decoder in order to assess their adequacy.