• 전기학회논문지P
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• 제58권4호
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• pp.538-540
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• 2009

The SBN thin films were deposited at substrate temperature of 300[$^{\circ}C$] on Pt-coated electrode (Pt/Ti/$SiO_2$/Si(100)) using RF sputtering method. The grain and crystallinity of SBN thin films were increased with the increase of annealing temperature. The dielectric constant(150) of SBN thin film was obtained by annealing temperature above 750[$^{\circ}C$]. The voltage dependence of dielectric loss showed a value within 0.01 in voltage ranges of -5~+5[V]. The capacitance characteristics showed a stable value of about 0.7[${\mu}F/cm^2$].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.440-443
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• 2000

The (Sr$_{1-x}$ Ca$_{x}$) thin films ale deposited OR Pt-Coated electrode(Pt/TiN/SiO$_2$/Si) using RF sputtering method with substitutional contents of Ca. The maximum grain of thin films is obtained at SCT15 thin film. The dielectric constant was increased with increasing the substitutional contents of Ca, while it was decreased if the substitutional contents of Ca exceeded over 15[mol%]. The temperature properties of the dielectric loss have a stable value within 2% independent of the substitutional contents of Ca.Ca.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.726-729
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• 2004

Etching characteristics of (Pb,Sr)$TiO_3$(PST) thin films were investigated using inductively coupled chlorine based plasma system as functions of gas mixing ratio, RF power and DC bias voltage. It was found that increasing of hi content in gas mixture lead to sufficient increasing of etch rate and selectivity of PST to Pt. The maximum etch rate of PST film is $562{\AA}/min$ and the selectivity of PST film to Pt is 0.8 at $Cl_2/(Cl_2+Ar)$ of 20 %. It was Proposed that sputter etching is dominant etching mechanism while the contribution of chemical reaction is relatively low due to low volatility of etching products.

• 한국전기전자재료학회논문지
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• 제30권8호
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• pp.484-490
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• 2017

We investigated the rewritable operation of a non-volatile memory device composed of Al (top)/$TiO_2$/indium-zinc-oxide (IZO)/Al (bottom). The oxygen-deficient IZO layer of the device was spin-coated with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions, and the $TiO_2$ layer was fabricated by atomic layer deposition. The oxygen vacancies IZO layer of an active component annealed at $400^{\circ}C$ using thermal annealing and it was proven to be in oxygen vacancies and oxygen binding environments with OH species and heavy metal ions investigated by X-ray photoelectron spectroscopy. The device, which operates at low voltages (less than 3.5 V), exhibits non-volatile memory behavior consistent with resistive-switching properties and an ON/OFF ratio of approximately $3.6{\times}10^3$ at 2.5 V.

• 센서학회지
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• 제4권4호
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• pp.75-80
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• 1995

금속 alkoxide를 출발물질로 PZT-PNN 3성분계 압전박막을 제작하여, 박막의 결정성과 전기적 특성을 평가하였다. 박막의 X-RD 분석결과 $550^{\circ}C$ 소결온도에서 결정성이 가장 양호하였다. D-E 이력곡선의 관측 결과 항전계는 28.8 kV/cm, 잔유분극은 $18.3\;{\mu}C/cm^{2}$ 이었다. 박막의 진성파괴전압은 $76.0\;{\sim}\;27.0\;MV/m$이었고, 소결온도가 상승함에 따라 특성이 저하되었다. 박막의 비유전율은 조성비에 따라 (50:40:10)은 406, (50:30:20)은 1084, (45:35:20)은 723, (40:40:20)은 316이었다.

• 융합정보논문지
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• 제7권5호
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• pp.123-128
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• 2017

나노구조를 갖는 물질들은 나노구조물이 갖는 고유의 체적 대비 높은 표면적 비와 양자 갇힘 효과에 기인하는 독특한 전기적, 광학적, 광전기적, 자기적 특성으로 인하여 많은 주목을 받아왔다. 열화학 기상 증착 공정은 나노 구조물의 성장과정에서 다양한 구조를 갖는 나노소재의 합성 능력 때문에 더욱 주목을 받아왔다. 본 연구에서는 두 영역 열화학 기상 증착법과 소스 물질 $TiO_2$ 파우더를 이용하여 VLS 공정으로 Si\$SiO_2$(300 nm)\Pt(5~40 nm) 기판 위에 실리콘 옥사이드 나노와이어를 성장시켰다. 성장된 실리콘 옥사이드 나노와이어의 형상과 결정학적 특성을 전계방출 주사전자현미경과 투과전자현미경으로 분석하였다. 분석결과, 성장된 실리콘 옥사이드 나노와이어의 형상인 지름과 길이는 촉매 박막의 두께에 의존하여 다른 모양을 나타내었다. 또한 성장된 실리콘 옥사이드 나노와이어는 비정질 상을 갖는 것으로 분석되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.489.2-489.2
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• 2014

The planar type flexible piezoelectric energy harvesters (PEH) based on PbZr0.52Ti0.48O3 (PZT) thin films on the flexible substrates are demonstrated to convert mechanical energy to electrical energy. The planar type energy harvesters have been realized, which have an electrode pair on the PZT thin films. The PZT thin films were deposited on double side polished sapphire substrates using conventional RF-magnetron sputtering. The PZT thin films on the sapphire substrates were transferred by PDMS stamp with laser lift-off (LLO) process. KrF excimer laser (wavelength: 248nm) were used for the LLO process. The PDMS stamp was attached to the top of the PZT thin films and the excimer laser induced onto back side of the sapphire substrate to detach the thin films. The detached thin films on the PDMS stamp transferred to adhesive layer coated on the flexible polyimide substrate. Structural properties of the PZT thin films were characterized using X-ray diffraction (XRD) and scanning electron microscopy (SEM). To measure piezoelectric power generation characteristics, Au/Cr inter digital electrode (IDE) was formed on the PZT thin films using the e-beam evaporation. The ferroelectric and piezoelectric properties were measured by a ferroelectric test system (Precision Premier-II) and piezoelectric force microscopy (PFM), respectively. The output signals of the flexible PEHs were evaluated by electrometer (6517A, Keithley). In the result, the transferred PZT thin films showed the ferroelectric and piezoelectric characteristics without electrical degradation and the fabricated flexible PEHs generated an AC-type output power electrical energy during periodically bending and releasing motion. We expect that the flexible PEHs based on laser transferred PZT thin film is able to be applied on self-powered electronic devices in wireless sensor networks technologies. Also, it has a lot of potential for high performance flexible piezoelectric energy harvester.

• 한국전기전자재료학회논문지
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• 제37권2호
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• pp.164-168
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• 2024

(La_0.7Sr_0.3)(Mn_1-xFe_x)O₃ (LSMFO) (x = 0.03, 0.06, 0.09, 0.12) precursor solution are prepared by sol-gel method. LSMFO thin films are fabricated by the spin-coating method on Pt/Ti/SiO₂/Si substrate, and the sintering temperature and time are 800℃ and 1 hr, respectively. The average thickness of the 6-times coated LSMFO films is about 181 to 190 nm and average grain size is about 18 to 20 nm. As the amount of Fe added in the LSMFO thin film increased, the resistivity decreased, and the TCR and B_25/65-value increased. Electrical resistivity, TCR and B_25/65-value of the (La_0.7Sr_0.3)(Mn_0.88Fe_0.12)O₃ thin film are 0.0136 mΩ-cm, 0.358%/℃, and 328 K at room temperature, respectively. The resistivity properties of LSMFO thin films matched well with Mott's VRH model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.