• 한국진공학회지
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• 제5권4호
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• pp.327-332
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• 1996

Tungsten(W) polycide gate 구조에서 $WSi_x$의 두께가 증가하면 열처리 공정 후 Gate oxide의 두께가 증가하며, 전기적 신뢰도가 열화 되는 현상이 발생한다. 이러한 특성 열화를 일으키는 지배적인 요인은 $WSi_x$ 증착 공정 중 유입되어 후속 열 공정에 의하여 gate oxide로 환산되는 fluorine인 것으로 밝혀졌다. 이러한 현상을 규명하기 위하여 fluorine ion implantation된 poly Si과의 특성을 비교하였으며, SIMS 및 단면 TEM을 이용한 미세 구조 연구를 실시하였다. 그러나 $WSi_x$의 두께가 600$\AA$ 이상부터는이러한 특성 열화가 포화되는 현상이 관찰되었다. 600$\AA$ 이상의 $WSi_x$ 두께에서는 미세 구조가 표면이 거칠고, porous한 phase로 구성된 상부 구조와 비교적 dense하고, 매끈한 계면 상태를 갖는 하부 구조로 이루어졌으며, porous한 표면 부위는 후속 열공정 중 oxygen-rich한 phase로 변하여 fluorine을 포획하여 oxide로의 확산을 억제하여 특성 열화가 포화되는 것으로 해석되었다.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.25-35
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• 2000

금속-산화막-반도체 소자의 산화막에 존재하는 느린 준위에 의한 전류반응 특성을 양방향 전류-전압 측정기술을 적용하여 분석하였다. 게이트 바이어스에 따라 나타나는 충전 및 방전시의 순간전류를 유지시간, 지연시간, 전자주입 방향 및 전자주입량, 그리고 전자 주입후 상온 방치시간의 함수로서 조사하였다. 느린 준위의 전하교환에 따른 전류 성분을 게이트 전압에 따라 실리콘 내 캐리어의 이동에 의해 나타나는 변위전류와 분리하여 해석하였다. 충전 및 방전시 나타나는 전하교환 전류는 산화막내 정전하 밀도뿐만 아니라 계면준위 밀도에도 크게 의존이 되며, 본 연구에서는 느린 준위의 전하교환 메카니즘을 제시하였다.

• 전자공학회논문지A
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• 제31A권7호
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• pp.85-94
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• 1994

A high-resolution transmission electron microscopy study of the solid phase crystallization of the amorphous silicon thin films, deposited on SiOS12T at 52$0^{\circ}C$ by low pressure chemical vapor deposition and annealed at 55$0^{\circ}C$ in a dry N$_{2}$ ambient was carried out so that the arrangement of atoms in the crystalline silicon and at the amorphous/crystalline interface of the growing grains could be understood on an atomic level. Results show that circular crystalline silicon nuclei have formed and then the grains grow to an elliptical or dendritic shape. In the interior of all the grains many twins whose{111} coherent boundaries are parallel to the long axes of the grains are observed. From this result, it is concluded that the twins enhance the preferential grain growth in the <112> direction along {111} twin planes. In addition to the twins. many defect such as intrinsic stacking faults, extrinsic stacking faults, and Shockley partial dislocations, which can be formed by the errors in the stacking sequence or by the dissociation of the perfect dislocation are found in the silicon grain. But neither frank partial dislocations which can be formed by the condensation of excess silicon atoms or vacancies and can form stacking fault nor perfect dislocations which can be formed by the plastic deformation are observed. So it is concluded that most defects in the silicon grain are formed by the errors in the stacking sequence during the crystallization process of the amorphous silicon thin films.

• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.179-183
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• 2005

A photodiode capable of obtaining a sufficient photo/ dark current ratio at both forward bias state and reverse bias state is proposed. The photodiode includes a glass substrate, an aluminum film formed as a lower electrode over the glass substrate, an alumina film formed as an insulator barrier over the aluminum film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the alumina film, and a transparent conduction film formed as an upper electrode over the hydro-generated amorphous silicon film. A good quality alumina $(Al_2O_3)$ film is formed by oxidation of aluminum film using electrolyte solution of succinic acid. Alumina is used as a potential barrier between amorphous silicon and aluminum. It controls dark-current restriction. In case of photodiodes made by changing the formation condition of alumina, we can obtain a stable dark current $(\~10^{-12}A)$ in alumina thickness below $1000{\AA}$. At the reverse bias state of the negative voltage in ITO (Indium Tin Oxide), the photo current has substantially constant value of $5{\times}10^{-9}$ A at light scan of 100 1x. On the other hand, the photo/dark current ratios become higher at smaller thicknesses of the alumina film. Therefore, the alumina film is used as a thin insulator barrier, which is distinct from the conventional concept of forming the insulator barrier layer near the transparent conduction film. Also, the structure with the insulator thin barrier layer formed near the lower electrode, opposed to the ITO film, solves the interface problem of the ITO film because it provides an improved photo current/dark current ratio.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• 한국재료학회지
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• 제4권7호
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• pp.750-758
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• 1994

본 연구에서는 반구형(HSG) 다결성 실리콘 박막을 제조하여 박막에 존재하는 결정립들의 특성과 각 결정립들의 형성기구를 예측하고자 하였다. LPCVD법으로 실리콘 박막을 증착하여 미세구조를 관찰, 분석한 결과 $575^{\circ}C$ 증착온도에서 HSG 다결정 실리콘 박막이 형성되었음을 관찰하였다. 이 HSG 박막은 비정질 및 결정질 상으로 구성되어 있었으며 결정립은 박막의 표면에 존재하는 upper grain들과 $SiO_{2}$와의계면에 존재하는 lower grain들로 구분되었다. Upper grain은 실리콘 원자의 표면확산에 의하여 형성되었으며, lower grain은 고상성장에 의하여 형성되었다. 성장한 결정립들의 성장방위를 분석한 결과 주로 upper grain은 <110>, lower grain은 <311>과 <111>방위를 나타내었다. 이러한 방위관계는 각 결정립들의 형성기구(formation mechanism)의 차이에 기인한다고 사료된다. 또한 HSG박막의 미세구조와 진공열처리한 시편을 관찰한 결과 HSG 박막의 형성은 실리콘 원자의 표면확산에 의해 지배됨을 알았다.

• Tribology and Lubricants
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• 제35권5호
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• 생태와환경
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• 제34권2호통권94호
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• pp.106-118
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• 2001

대청호내 3개 지점에서 저토의 영양염을 조사하여 수층과 식물플랑크톤에 대한 생장 잠재력에 미치는 영향을 파악하였다. 저토-수층의 경계면에서 DO는 0.5 mg $O_{2}$/l 이하로서 무산소 상태였다. 공극수의 전기전도도는 저토보다 1.9${\sim}$2.6배 더 높았고 수심이 얕을수록 변동폭이 컸다. Eh는 -12${\sim}$-148mV 범위였고 가비중은 1.17${\sim}$1.30g/cm$^{3}$ 범위로서 지역간에 차이가 크지 않았다. 함수율과 유기물 함량은 각각 58%${\sim}$72%, 8${\sim}$13% 범위로서 댐 부근에서 높았고 옥천천에서 낮았다. 저토의 입도 조성은 사질이 97%를 차지하였다. 저토내 총세균수와 규조류의 세포밀도는 수심이 깊은 하류에서 높았다. 공극수와 치환성의 질소와 인 함량에서 입자성이 용존성보다 풍부하였고, 무기 질소로는 NH$_{4}$가 대부분이었다. 또한 유기와 무기 질소 형태로 볼 때, 공극수내 질소함량은 무기 질소가 많았고, 치환성 질소는 유기 질소가 많았다. 공극수 인 함량에서 용존 유기 인이 많았고 치환성은 무기 인이 많았다. 저토내 규소는 치환성이 최대 63%로서 공극수보다 훨씬 많았다. 대청호의 저토는 유기물이 풍부한 부영양 상태로 평가되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.23-23
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• 2009

GaN-based nitride semiconductors have attracted considerable attention in high-brightness light-emitting-diodes (LEDs) and laser diodes (LDs) covering from green to ultraviolet spectral range. LED and LD heterostructures are usually grown on (0001)-$Al_2O_3$. The large lattice mismatch between $Al_2O_3$ substrates and the GaN layers leads to a high density of defects(dislocations and stacking faults). Moreover, Ga and N atoms are arranged along the polar [0001] crystallographic direction, which leads to spontaneous polarization. In addition, in the InGaN/GaN MQWs heterostructures, stress applied along the same axis can also give rise to piezoelectric polarization. The total polarization, which is the sum of spontaneous and piezoelectric polarizations, is aligned along the [0001] direction of the wurtzite heterostructures. The change in the total polarization across the heterolayers results in high interface charge densities and spatial separation of the electron and hole wave functions, redshifting the photoluminescence peak and decreasing the peak intensity. The effect of polarization charges in the GaN-based heterostructures can be eliminated by growing along the non-polar [$11\bar{2}0$] (a-axis) or [$1\bar{1}00$] (m-axis) orientation instead of thecommonly used polar [0001] (c-axis). For non-polar GaN growth on non-polar substrates, the GaN films have high density of planar defects (basal stacking fault BSFs, prismatic stacking fault PSFs), because the SFs are formed on the basal plane (c-plane) due to their low formation energy. A significant reduction in defect density was recently achieved by applying blocking layer such as SiN, AlN, and AlGaN in non-polar GaN. In this work, we were performed systematic studies of the defects in the nonpolar GaN by conventional and high-resolution transmission electron microscopy.

• 마이크로전자및패키징학회지
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• 제28권1호
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• pp.39-46
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• 2021

Cu 배선(interconnect) 적용을 위한 다층박막의 적층 구조에 따른 최적 계면접착에너지(interfacial adhesion energy, Gc) 평가방법을 도출하기 위해, Ta, Cu 및 tetraethyl orthosilicate(TEOS-SiO2) 박막 계면의 정량적 계면접착에너지를 double cantilever beam(DCB) 및 4-점 굽힘(4-point bending, 4-PB) 시험법을 통해 비교 평가하였다. 평가결과, Ta확산방지층이 적용된 시편(Cu/Ta, Cu/Ta/TEOS-SiO2)에서는 두 가지 평가방법 모두 반도체 전/후 공정에서 박리가 발생하지 않는 산업체 통용 기준인 5 J/㎡ 보다 높게 측정되었다. Ta/Cu 시편의 경우 DCB 시험에서만 5 J/㎡ 보다 낮게 측정되었다. 또한, DCB시험 보다 4-PB시험으로 측정된 Gc가 더 높았다. 이는 계면파괴역학 이론에 따라 이종재료의 계면균열 선단에서 위상각의 증가로 인한 계면 거칠기 및 소성변형에 의한 에너지 손실이 증가 하는것에 기인한다. 4-PB시험결과, Ta/Cu 및 Cu/Ta계면은 5 J/㎡ 이상의 높은 계면접착에너지를 보이므로, 계면접착에너지 관점에서는 Ta는 Cu배선의 확산방지층(diffusion barrier layer) 및 피복층(capping layer)으로 적용 가능할 것으로 생각된다. 또한, 배선 집적공정 및 소자의 사용환경에서 열팽창 계수 차이에 의한 열응력 및 화학적-기계적 연마 (chemical mechanical polishing)에 의한 박리는 전단응력이 포함된 혼합모드의 영향이 크므로 4-PB 시험으로 측정된 Gc와 연관성이 더 클 것으로 판단된다.