• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.195-200
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• 1998

We have investigated the crystal structure and electrical properties of Pt/SBT/$CeO_2$/Si(MFIS) and Pt/SBT/Si(MFS) structures for the gate oxide of ferroelectric memory. XRD spectra and SEM showed that the SBT film of SBT/$CeO_2$/Si structure had larger grain than that of SBT/Si structure. Furthermore HRTEM showed that SBT/$CeO_2$/Si had 5 nm thick $SiO_2$layer and very smooth interface but SBT/Si had 6nm thick $SiO_2$layer and 7nm thick amorphous intermediate interface. Therefore, $CeO_2$film between SBT film and Si substrate is confirmed as a good candidate for a diffusion barrier. The remanent polarization decreased and coercive voltage increased in Pt/SBT/$CeO_2/Pt/SiO_2$/Si structure. This effect may increase memory window of MFIS structure directly related to the coercive voltage. From the capacitance-voltage characteristics, the memory of Pt/SBT(140 nm)/$CeO_2$(25 nm)/Si structure were in the range of 1~2 V at the applied voltage of 4~6 V. The memory window increased with the thickness of SBT film. These results may be due to voltage applied at SBT films. The leakage currents of Pt/SBT/$CeO_2$/Si and Pt/SBT/Si were $ 10^8A/\textrm{cm}^2$ and $ 10^6 A/\textrm{cm}^2$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.436-439
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• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• Journal of IKEEE
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• v.18 no.4
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• pp.620-624
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• 2014

In this study, the electrical characteristics of Ni/CNT/$SiO_2$ structures were investigated in order to analyze the mechanism of carbon nanotubes in 4H-SiC MIS device structures. We fabricated 4H-SiC MIS capacitors with or without carbon nanotubes. Carbon nanotubes were dispersed by isopropyl alcohol. The capacitance-voltage (C-V) is characterized at 300 to 500K. The experimental flat-band voltage ($V_{FB}$) shift was positive. Near-interface trapped charge density and oxide trapped charge density values of Ni/CNT/$SiO_2$ structure were less than values of reference samples. With increasing temperature, the flat-band voltage was negative. It has been found that its oxide quality is related to charge carriers or defect states in the interface of 4H-SiC MIS capacitors. Gate characteristics of 4H-SiC MIS capacitors can be controlled by carbon nanotubes between Ni and $SiO_2$.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.118-119
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• 2007

Phase stability and morphological investigation on the $Si/SiO_2/HfO_2$ and $Si/SiO_2/ZrO_2$ stack are presented. Thermal stability of $HfO_2$ and $ZrO_2$ determines the quality of interface and subsequently the performance of device. The stacks have been fabricated and annealed at $1000^{\circ}C$ for various time. In evolution of crystalline phase and morphology (electrical and geometrical) of high-k materials, annealing time and process are observed to be crucial factors. The crystallization of some phase has been observed in the case of $Si/SiO_2/HfO_2$. The chemical environment around Zr and Hf in respective samples is observed to be different.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.112-112
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• 1996

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.128.1-128.1
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• 2016

Nitrided-metal gates on the high-${\kappa}$ dielectric material are widely studied because of their use for sub-20nm semiconductor devices and the academic interest for the evanescent states at the Si/insulator interface. Issues in these systems with the Si substrate are the electron mobility degradation and the reliability problems caused from N defects that permeates between the Si and the $SiO_2$ buffer layer interface from the nitrided-gate during the gate deposition process. Previous studies proposed the N defect structures with the gap states at the Si band gap region. However, recent experimental data shows the possibility of the most stable structure without any N defect state between the bulk Si valence band maximum (VBM) and conduction band minimum (CBM). In this talk, we present a new type of the N defect structure and the electronic structure of the proposed structure by using the first-principles calculation. We find that the pair structure of N atoms at the $Si/SiO_2$ interface has the lowest energy among the structures considered. In the electronic structure, the N pair changes the eigenvalue of the silicon-induced gap state (SIGS) that is spatially localized at the interface and energetically located just above the bulk VBM. With increase of the number of N defects, the SIGS gradually disappears in the bulk Si gap region, as a result, the system gap is increased by the N defect. We find that the SIGS shift with the N defect mainly originates from the change of the kinetic energy part of the eigenstate by the reduction of the SIGS modulation for the incorporated N defect.

• Journal of the Korean Ceramic Society
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• v.51 no.5
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• pp.459-465
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• 2014

In this study, Si-SiC composites were fabricated using a Si melt infiltration method using ${\beta}$-SiC/C composite powders synthesized by the carbothermal reduction of $SiO_2-C$ precursors made from a TEOS and a phenol resin. The purity of the synthesized SiC-C composite powders was higher than 99.9993 wt% and the average particle size varied from 4 to $6{\mu}m$ with increasing carbon contents of the $SiO_2-C$ precursors. It was found that the Si-SiC composites fabricated in this study consist of ${\beta}$-SiC and residual Si, without any trace of ${\alpha}$-SiC. The 3-point bending strengths of the fabricated Si-SiC composites were measured and found to be higher than 550 MPa, although the density of the fabricated Si-SiC composite was less than $2.9g/cm^3$. The bending strengths and the densities of the fabricated Si-SiC composites were found to decrease with increasing C/Si mole ratios in the SiC-C composite powders. The specific resistivities of the Si-SiC composites fabricated using the SiC-C composite powders were less than $0.018{\Omega}cm$. With increasing C content in the SiC-C composite powders used for the fabrication of Si-SiC composites, the specific resistivity of the Si-SiC composites was found to slightly increase from 0.0157 to $0.018{\Omega}cm$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.