• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.209.2-209.2
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• 2015

Two dimensional layered materials, such as transition metal dichalcogenides (TMDs) family have been attracted significant attention due to novel physical and chemical properties. Among them, molybdenum disulfide ($MoS_2$) has novel physical phenomena such as absence of dangling bonds, lack of inversion symmetry, valley degrees of freedom. Previous studies have shown that the interface of metal/$MoS_2$ contacts significantly affects device performance due to presence of a scalable Schottky barrier height at their interface, resulting voltage drops and restricting carrier injection. In this study, we report a new device structure by using few-layer graphene as the bottom interconnections, in order to offer Schottky barrier free contact to bi-layer $MoS_2$. The fabrication of process start with mechanically exfoliates bulk graphite that served as the source/drain electrodes. The semiconducting $MoS_2$ flake was deposited onto a $SiO_2$ (280 nm-thick)/Si substrate in which graphene electrodes were pre-deposited. To evaluate the barrier height of contact, we employed thermionic-emission theory to describe our experimental findings. We demonstrate that, the Schottky barrier height dramatically decreases from 300 to 0 meV as function of gate voltages, and further becomes negative values. Our findings suggested that, few-layer graphene could be able to realize ohmic contact and to provide new opportunities in ohmic formations.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Journal of Korea Foundry Society
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• v.13 no.6
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• pp.547-554
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• 1993

Aluminum alloy matrix composites reinforced with various amounts of $Al_2O_3$ short fibers have been produced by rheo-compocasting accompanied by hot pressing. When composites reinforced with fibers are produced by rheo-compocasting, S-L process is the most effective method for homogeneous dispersion of fibers. A sound composites with the improved orientation(3 dimension${\rightarrow}$2 dimension) of the fibers and increased volume fraction of them have been fabricated through the hot pressing of the casted composites. Fibers are broken down when rheo-compocasting, hot pressing, and $T_6$ treating. Among them fibers are broken down most heavily in the hot pressing. And even in the case of the composite reinforced with 30 vol% fibers, which showed the hardest fiber break down, aspect ratio(11.6) is higher than critical aspect ratio(10.7). The fiber strengthening effect in the composites has showed upto 573K. As the test temperature increases to the range of 573K, the effect has been higher. The fracture of composites is controlled by fiber from room temperature to 473K, but the fracture of composites is controlled by interface between fiber and matrix alloy above 473K.

• Journal of the Mineralogical Society of Korea
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• v.26 no.2
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• pp.119-127
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• 2013

Borosilicate glass dissolution is an important chemical process that impacts the glass durability as nuclear waste form that may be used for high-level radioactive waste disposal. Experiments reported that the glass dissolution rates are strongly dependent on the bulk composition. Because some relationship exists between glass composition and molecular-structure distribution (e.g., non-bridging oxygen content of $SiO_4$ unit and averaged coordination number of B), the composition-dependent dissolution rates are attributed to the bulk structural changes corresponding to the compositional variation. We examined Na borosilicate glass structures by performing classical molecular dynamics (MD) simulations for four different chemical compositions ($xNa_2O{\cdot}B_2O_3{\cdot}ySiO_2$). Our MD simulations demonstrate that glass surfaces have significantly different chemical compositions and structures from the bulk glasses. Because glass surfaces forming an interface with solution are most likely the first dissolution-reaction occurring areas, the current MD result simply that composition-dependent glass dissolution behaviors should be understood by surface structural change upon the chemical composition change.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• Journal of the Korean institute of surface engineering
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• v.36 no.1
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• pp.14-21
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• 2003

Thin films of ZrO$_2$ and TiO$_2$ were deposited on Si(100) substrates using RF magnetron sputtering technique. To study an influence of the sputtering parameters, systematic experiments were carried out in this work. XRD data show that the $ZrO_2$ films were mainly grown in the [111] orientation at the annealing temperature between 800 and $1000^{\circ}C$ while the crystal growth direction was changed to be [012] at above $1000^{\circ}C$. FT-IR spectra show that the oxygen stretching peaks become strong due to $SiO_2$ layer formation between film layers and silicon surface after annealing, and proved that a diffusion caused by either oxygen atoms of $ZrO_2$ layers or air into the interface during annealing. Different crystal growth directions were observed with the various deposition parameters such as annealing temperature, RF power magnitude, and added $O_2$ amounts. The growth rate of $TiO_2$ thin films was increased with RF power magnitude up to 150 watt, and was then decreased due to a sputtering effect. The maximum growth rate observed at 150 watt was 1500 nm/hr. Highly oriented, crack-free, stoichiometric polycrystalline $TiO_2$<110> thin film with Rutile phase was obtained after annealing at $1000^{\circ}C$ for 1 hour.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.9
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• pp.695-699
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• 2001

Cerium dioxide (CeO$_2$) was used as the intermediate layer between the ferroelectric thin film and Si substrate in a metal-ferroelectric-semiconductor field effect transistor (MFSFET), to improve the interface property by preventing the interdiffusion of the ferroelectric material and the Si substrate. In this study, CeO$_2$ thin films were etched with a CF$_4$/Ar gas combination in inductively coupled plasma (ICP). The maximum etch rate of CeO$_2$ thin films was 270$\AA$/min under CF$_4$/(CF$_4$+Ar) of 0.2, 600 W/-200V, 15 mTorr, and $25^{\circ}C$. The selectivities of CeO$_2$ to PR and SBT were 0.21, 0.25, respectively. The surface reaction in the etching of CeO$_2$ thin films was investigated with x-ray photoelectron spectroscopy (XPS). There is a chemical reaction between Ce and F. Compounds such as Ce-F$_{x}$ remains on the surface of CeO$_2$ thin films. Those products can be removed by Ar ion bombardment. The results of secondary ion mass spectrometry (SIMS) were consistent with those of XPS. Scanning electron microscopy (SEM) was used to examine etched profiles of CeO$_2$ thin films. The etch profile of over-etched CeO$_2$ films with the 0.5${\mu}{\textrm}{m}$ line was approximately 65$^{\circ}$.>.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.218-224
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• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

• Resources Recycling
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• v.15 no.2 s.70
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• pp.3-9
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• 2006

As a basic study on the conversion of molten converter slag to the ordinary portland cement, the effects of $Al_{2}O_{3}$ addition on the interface reaction between solid CaO and molten converter slag has been studied. Alumina added converter slag whose basicity was controlled to 1 and 2 was melted and hold for 30 minutes in MgO crucible at $1500^{\circ}C$. Then sintered CaO pellet heated at the same temperature was dipped into the molten slag and held for 30minutes. After the reaction, the crucible was cooled in air and the specimen was cut off to the horizontal direction of the crucible. The dissolution rate of CaO pellet with the addition of $Al_{2}O_{3}$ was measured by the change of the radius or sintered CaO pellet and the interface layer was observed by SEM/EDX. As a result. At the basicity 2 slag, thickness of created $C_{3}S$ layer increased 3.5 times and quantity of $C_{6}AF_{2}\;or\;C_{4}AF$ phase increase 2 times than baisicy 1 slag.