• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
• /
• v.16 no.2
• /
• pp.173-182
• /
• 2018

As part of planning for waste minimization, decontamination foam has been considered as a potential application for the cleaning of radioactive contaminant. In this study, we synthesized silica particles to improve foam stability by varying synthesis parameters. Cetyltrimethylammonium bromide (CTAB) was found to influence the stability of the decontamination foam. The reason was that higher interaction between $SiO_2$ nanoparticles and surfactant at the air-water interface in aqueous solution is beneficial for foam stability. CTAB can also be used as an additive for the aggregation of silica nanoparticles. In the separation of $SiO_2$ nanoparticles, CTAB plays a critical role in the nanoparticles flocculation because of the charge neutralization and hydrophobic effects of its hydrocarbon tails.

• Korean Journal of Materials Research
• /
• v.8 no.10
• /
• pp.912-917
• /
• 1998

화학적 산화막(SiOx)이 형성된 Si(100)기판 위에 Co-silicide의 형성과 계면 형상에 관한 연구를 하였다. 화학적 산화막은 과산화수소수(H2O2)의 인위적 처리에 의해 약 2nm을 형성시켰다. 그 위에 5nm 두께의 Co 박막을 전자빔 증착기에 의해 증착시킨 후 열처리하여 Co-silicide를 형성하였다. 화학적 산화막 위에서 Co-silicide 반응기구를 알아 보기 위해 $500^{\circ}C$-$900^{\circ}C$의 온도 범위에서 ex-situ와 in-situ 열처리를 하였다. 이와같이 형성된 Co-silicide 시편의 상형성, 표면 및 계면 형상, 그리고 화학적 조성을 XRD, SEM, TEM, 그리고 AES를 이용하여 분석하였다. 분석 결과 es-situ 열처리시 $700^{\circ}C$까지 CoSi2 상은 형성되지 않았고 Co의 응집화현상이 일어났다. $800^{\circ}C$ 열처리한 경우에는 CoSI2가 형성되었고 facet 현상이 크게 나타났으며 불연속적인 grain 들이 형성되었다. In-situ 열처리한 경우에는 저온에서 ($550 ^{\circ}C$)반응하여 Co-silicide가 형성되기 시작하였으며 $600^{\circ}C$부터는 facet에 의해 박막의 특성이 나빠지기 시작했다. $550^{\circ}C$에서 Co가 화학적 산화막 층을 통해 확산하여 균질한 Co-silicide를 형성하였다. 이와같이 형성된 균질한 실리사이드 층을 이용하여 다단계(55$0^{\circ}C$-$650^{\circ}C$-$800^{\circ}C$)열처리에 의해 균질한 다결정 CoSI2의 형성이 관찰되었다.

• Korean Journal of Materials Research
• /
• v.1 no.4
• /
• pp.229-235
• /
• 1991

A new electrode material for $Ta_2O_5$ capacitor was developed to obtain both high dielectric constant and improved electrical properties for use in DRAM. High leakage current and low breakdown field of as-deposited $Ta_2O_5$ film on Si is due to the reduction of $Ta_2O_5$ by silicon at $Ta_2O_5$/electrode interface. $Dry-O_2$ anneal improves the electrical properties of $Ta_2O_5$ capacitor with Si electrode, but it thickens the interfacial oxide and lowers the dielectric constant, subsequently. $Ta_2O_5$ capacitor with TiN exectrode shows better electrical properties and higher dielectric constant than post heat treated $Ta_2O_5$ film on Si. No interfacial oxide layer at $Ta_2O_5$/TiN interface suggests that there\`s no Interaction between $Ta_2O_5$ and electrode. TiN is a adequate electrode material for $Ta_2O_5$ capacitor.

• Electrical & Electronic Materials
• /
• v.1 no.3
• /
• pp.269-277
• /
• 1988

P형 Si(100)로 제작한 MOS 커패시터에 $Co^{60}$-.gamma.선을 주사한 후 고주파 C-V특성 곡선으로 부터 방사선 조사에 의해 유발된 산화막안의 트랩전하의 거동 및 Si- $SiO_{2}$계면에서의 트랩밀도 분포의 변화를 검토하였다. 산화막 느랩전하는 .gamma.선 흡수선량 증가와 더불어 증가하다가 $10^{7}$ rad 부근에서부터 서서히 포화하는 경향이 나타났으며 게면트랩밀도의 분포모양은 흡수선량의 증가와 더불어 전형적인 이그러진 W자형에서 넓혀진 V자형 분포로 변화하였으나 최소값은 항상 진성페르미준위( $E_{i}$)부근에 있었으며 그 밀도는 1.0*$10^{11}$~7.5*$10^{11}$[개/$cm^{2}$/eV]로 계산되었다. 또한, 일정 바이어스전압하에서의 조사선량에 따른 $V_{fb}$ 의 변화는 현저하지는 않았으나 바이어스 전압을 +12V로 인가할 때 변화방향의 반전상태가 관측되었다. 그 이유로는 Si측의 계면 부근에서 일어난 눈사태 전자가 산화막내로 주입됨에 따라 도너형 양전하의 수가 감소되기 때문으로 추정되었다.되었다.

• Journal of Astronomy and Space Sciences
• /
• v.22 no.4
• /
• pp.483-490
• /
• 2005

For an image sensor CCD, electrons can be trapped at the front-side $Si-SiO_2$ surface interface in a case of exceeding the full well by bright source. Residual images can be made by the electrons remaining in the interface. These residual images are seen in the font-side-illuminated CCDs especially. It is not easy to find a quantitative analysis for this phenomenon in the domestic reports, although it is able to contaminate observation data. In this study, we find residual images iB dark frames which were obtained from the front-side-illuminated CCD at Mt. Lemmon Optical Astronomy Observatory (LOAO), and analyze the effect to contaminated observation data by residual charges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.354-357
• /
• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.3
• /
• pp.135-140
• /
• 2018

Atomically thin $MoS_2$ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, $MoS_2$ single-crystal as a transistor channel after transfer onto a $SiO_2/Si$ substrate. The $MoS_2$ FETs displayed n-channel characteristics with an electron mobility of $0.05cm^2/V-sec$, and a current on/off ratio of $I_{ON}/I_{OFF}{\simeq}5{\times}10^4$. Application of bottom-gate voltage stresses, however, increased the interface charges on $MoS_2/SiO_2$, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

• Korean Journal of Materials Research
• /
• v.3 no.4
• /
• pp.403-409
• /
• 1993

In this paper, an $NH_3$, added during dry oxidation and annealing m Si( 111) is clarified effect ive to suppress or remove defects. Annealing effects in $N_2$ and $NH_3/N_2$ ambient are estimated with dry $O_2$ and $NH_4$ oxidation($NH_3$ added in dry $O_2$ oxidation) method. C;em'rated defects in dry $O_2$ oxidation are lengthened according to oxidation time. but any defects in $NH_3$ oxidation are not found. Dry oxidation, after $NH_3$ oxidation as an initial oxidation. lias the defect -removing effect at the interface of Si -$SiO_2$. After dry or $NH_3$. oxidation. the annealmg 7.5% $NH_3/N_2$ ambient brings out gettering effect of OSF. The annealing in 7.5% $NH_3/N_2$ ambient for NI L oxidation method decreaSE,s $NH_3$ length of OSF about 20 % compared with dry oxidation method. Tlw feature of OSF is pit type, the gettering is directed to (011) plane for (111) plane. and OSFs are etched following to 110) directIon.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.40-43
• /
• 2000

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.11a
• /
• pp.453-456
• /
• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.