• 신재생에너지
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• 제18권1호
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• pp.29-34
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• 2022

The most prevalent cause of solar cell efficiency loss is reduced recombination at the metal electrode and silicon junction. To boost efficiency, a a SiO_X/poly-Si passivating interface is being developed. Poly-Si for passivating contact is formed by various deposition methods (sputtering, PECVD, LPCVD, HWCVD) where the ploy-Si characterization depends on the deposition method. The sputtering process forms a dense Si film at a low deposition rate of 2.6 nm/min and develops a low passivation characteristic of 690 mV. The PECVD process offers a deposition rate of 28 nm/min with satisfactory passivation characteristics. The LPCVD process is the slowest with a deposition rate of 1.4 nm/min, and can prevent blistering if deposited at high temperatures. The HWCVD process has the fastest deposition rate at 150 nm/min with excellent passivation characteristics. However, the uniformity of the deposited film decreases as the area increases. Also, the best passivation characteristics are obtained at high doping. Thus, it is necessary to optimize the doping process depending on the deposition method.

• 센서학회지
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• 제5권6호
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• pp.60-67
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• 1996

저온 remote PECVD $SiO_{2}$막을 이용하여 제조된 InSb MIS구조에서의 계면의 전기적 특성에 대하여 연구하였다. $105^{\circ}C$에서 증착시킨 $SiO_{2}$막을 이용한 MIS구조의 중간 에너지 대역폭에서의 계면상태밀도가 $1{\sim}2{\times}10^{11}\;cm^{-2}eV^{-1}$으로 평가되었다. 그러나, $105^{\circ}C$이상의 고온에서 제조된 MIS소자의 계면에는 다량의 계면준위 및 트랩 준위가 존재하였다. G-V측정으로부터 계산된 계면준위들의 시상수는 $10^{-4}{\sim}10^{-5}\;sec$였으며, 증착온도가 증가할수록 트랩밀도가 증가하여 C-V특성곡선의 이력특성이 증대되었다.

• 센서학회지
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• 제23권6호
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• pp.392-396
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• 2014

The 2-dimensional silicon vertical Hall devices, which are sensitive to X,Y components of the magnetic field parallel to the surface of the chip, are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$ interface and n-epi layer to improve the sensitivity and influence of interface effect. Experimental samples are a sensor type K with and type J without $p^+$ isolation dam adjacent to the center current electrode. The results for both type show a more high sensitivity than the former's 2-dimensional vertical Hall devices and a good linearity. The measured non-linearity is about 0.8%. The sensitivity of type J and type K are about 66 V/AT and 200 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.361-366
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• 2004

The interface stability of Ta-Mo alloy film on SiO$_2$ was investigated. Ta-Mo alloy films were formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power, When the atomic composition of Ta was about 91％, the measured work function was 4.24 eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy film and SiO$_2$, C-V and XRD measurements were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and 90$0^{\circ}C$. Even after 90$0^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 추계학술대회 초록집
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• pp.47.2-47.2
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• 2011

High-efficient transparent conductive oxide (TCO) film-embedding Si heterojunction solar cells were fabricated. An improved crystalline indium-tin-oxide (ITO) film was grown on an Al-doped ZnO (AZO) template upon hetero-epitaxial growth. This double TCO-layered Si solar cell provided significantly enhanced efficiency of 9.23 % as compared to the single TCO/Si devices. The effective arrangement of TCO films (ITO/AZO) provides a good interface, resulting in the enhanced photovoltaic performances. It discusses TCO film arrangement scheme for efficient TCO-layered heterojunction solar cells.

• 한국조명전기설비학회지:조명전기설비
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• 제6권2호
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• pp.51-55
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• 1992

In this study as treating to filter silance coupling agent (KM-6030 improving coupling strength between matrix resin (bisphenole-A type epoxy resin) and filler (SiO2), breakdown strength was investigated on cases applying DC voltage to specimen. In the case on DC voltage, breakdown strength was improved bout 12.73% and 10.77% in specimen of 5[wt%] and 50[wt%] of filler content of 10 of epoxy. Therefore, it was investigate the effect that concentration of coupling agent and content of filler was influential on breakdown strength of epoxy resin.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1997년도 제12회 학술발표회 논문개요집
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• pp.173-173
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• 1997

• 한국진공학회지
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• 제1권1호
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• pp.67-72
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• 1992

고에너지 반사 전자회절기(RHEED) 및 투과전자현미경(HRTEM)을 이용하여 Si(111)-7 $\times$ 7 면에서의 Ti 박막의 성장 mode와 Si(111) 면에서의 C54 TiSi2의 정합성장 을 조사하였다. 초고진공에서 Si(111)-7 $\times$ 7 표면에 상온에서 Ti를 증착하면 Ti/Si 계면에 서 비정질의 Ti-Si 중간막이 먼저 형성되고 그 위에 Ti 박막은 다결정으로 성장하였다. 160ML의 Ti를 증착한 시료를 초고진공 내에서 75$0^{\circ}C$로 10분 열처리하면 C54 TiSi2가 정합 성장하였으며 이는 HRTEM 격자상 및 TED Pattern으로 확인할 수 있었다. TiSi2/Si(111) 시 료를 다시 $900^{\circ}C$로 가열하면 TiSi2위에 단결정 Si층이 [111] 방향으로 성장하였다.

• 한국재료학회지
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• 제25권9호
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• pp.429-434
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• 2015

Resistance switching memory cells were fabricated using atomically dispersed Pt-$SiO_2$ thin film prepared via RF co-sputtering. The memory cell can switch between a low-resistance-state and a high-resistance-state reversibly and reproducibly through applying alternate voltage polarities. Percolated conducting paths are the origin of the low-resistance-state, while trapping electrons in the negative U-center in the Pt-$SiO_2$ interface cause the high-resistance-state. Intermediate resistance-states are obtained through controlling the compliance current, which can be applied to multi-level operation for high memory density. It is found that the resistance value is related to the capacitance of the memory cell: a 265-fold increase in resistance induces a 2.68-fold increase in capacitance. The exponential growth model of the conducting paths can explain the quantitative relationship of resistance-capacitance. The model states that the conducting path generated in the early stage requires a larger area than that generated in the last stage, which results in a larger decrease in the capacitance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1646-1648
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• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.