• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.9-14
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• 2017

$ISnO_2$ thin films were prepared on p-type and n-type Si substrates to research the interface characteristics between $SnO_2$ and substrate. After the annealing processes, the amorphous structure was formed at the interface to make a Schottky contact. The O 1s spectra showed the bond of 530.4 eV as an amorphous structure, and the Schottky contact. The analysis by the deconvoluted spectra was observed the drastic variation of oxygen vacancies at the amorphous structure because of the depletion layer is directly related to the oxygen vacancy. $SnO_2$ thin film changed the electrical properties depending on the characteristics of substrates. It was confirmed that it is useful to observe the Schottky contact's properties by complementary using the XPS analysis and I-V measurement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.436-441
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• 1998

$Pt/SrTiO_3/Pb_x(Zr_{0.52}, Ti_{0.48})O_3/SrTiO_3/Si$ structure was prepared by rf-magnetron sputtering method for use in nondestructive read out ferroelectric RAM(NDRO-FEAM). PBx(Zr_{0.52}Ti_{0.48})O_3}$(PZT) and $SrTiO_3$(STO) films were deposited respectively at the temperatures of $300^{\circ}C and 500^{\circ}C$on p-Si(100) substrate. The role of the STO film as a buffer layer between the PZT film and the Si substrate was studied using X-ray diffraction (XRD), Auger electron spectroscopy (ASE), and scanning electron microscope(SEM). Structural analysis on the interfaces was carried out using a cross sectional transmission electron microscope(TEM). For PZT/Si structure, mostly Pb deficient pyrochlore phase was formed due to the serious diffusion of Pb into the Si substrate. On the other hand, for STO/PZT/STO/Si structure, the PZT film had perovskite phase and larger grain size with a little Pb interdiffusion. the interfaces of the PZT and the STO film, of the STO film and the interface layer and $SiO_2$, and of the $SiO_2$ and the Si substate had a good flatness. Across sectional TEM image showed the existence of an amorphous layer and $SiO_2$ with 7nm thickness between the STO film and the Si substrate. The electrical properties of MIFIS structure was characterized by C-V and I-V measurements. By 1MHz C-V characteristics Pt/STO(25nm)/PZT(160nm)/STO(25nm)/Si structure, memory window was about 1.2 V for and applied voltage of 5 V. Memory window increased by increasing the applied voltage and maximum voltage of memory window was 2 V for V applied. Memory window decreased by decreasing PZT film thickness to 110nm. Typical leakage current was abour $10{-8}$ A/cm for an applied voltage of 5 V.

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.35.1-35
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• 2003

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.57-61
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• 2011

To develop high efficiency crystalline solar cells, the rear surface passivation is very important. In this paper, $Al_2O_3$ films deposited by thermal ALD(atomic layer deposition) method were studied for rear surface passivation of crystalline solar cells and their passivation properties were evaluated. After the deposition of $Al_2O_3$ films on p-type Si wafers, the lifetime was increased very much due to the reduction of interface state density and the field effects of the negative fixed charge in the films. Also, optimum annealing condition and effects of SiNx capping layer were investigated. The best lifetime was obtained when the films were annealed at $400^{\circ}C$ for 15min. And the lifetime degradation of the $Al_2O_3$ films with SiNx capping layers was improved compared to those without the capping layers.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.64-67
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• 2000

Tungsten silicide(WSi$_2$) is proposed for the alternate gate electrode of ULSI MOS devices. Good structural property and low resistivity of WSi$_2$ deposited by a low pressure chemical vapor deposition(LPCVD) method directly on SiO$_2$ is obtained after annealing. Especially, WSi$_2$-SiO2 interface remains flat after annealing tungsten silicide at high temperature. Electrical characteristics of annealed WSi$_2$-SiO$_2$-Si(MOS) capacitors were improved in view of charge trapping.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.230-230
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• 2013

In amorphous or microcrystalline thin-film silicon solar cells, p-i-n structure is used instead of p/n junction structure as in wafer-based Si solar cells. Hence, these p-i-n structured solar cells inevitably consist of many interfaces and the cell efficiency critically depends on the effective control of these interfaces. In this study, in-situ plasma treatment process of the interfaces was developed to improve the efficiency of a-Si:H solar cell. The p-i-n cell was deposited using a single-chamber VHF-PECVD system, which was driven by a pulsed-RF generator at 80 MHz. In order to solve the cross-contamination problem of p-i layer, high RF power was applied without supplying SiH4 gas after p-layer deposition, which effectively cleaned B contamination inside chamber wall from p-layer deposition. In addition to the p-i interface control, various interface control techniques such as thin layer of TiO2 deposition to prevent H2 plasma reduction of FTO layer, multiple applications of thin i-layer deposition and H2 plasma treatment, H2 plasma treatment of i-layer prior to n-layer deposition, etc. were developed. In order to reduce the reflection at the air-glass interface, anti-reflective SiO2 coating was also adopted. The initial solar cell efficiency over 11% could be achieved for test cell area of 0.2 $cm^2$.

• Korean Journal of Materials Research
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• v.10 no.10
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• pp.684-690
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• 2000

In order to study effects of interfacial layers between $Pb(Zr,Til)Q_3(PZT)$ films and electrodes for Metal-Ferroelectric-MetaI(MFM) structure capacitors, we have fabricated the capacitors with the Pt/PZT/interfacial-layer/Pt/$TiO_2/SiO_2$/Si structure. $PbTiO_3(PT)$ interfacial layers were formed by sol-gel deposition and PbO, ZrO, and $TiO_2$ thin layers were deposited by reactive sputtering. $TiO_2$ interface layers result in the finest grains of PZT(crystalline Temp. $600^{\circ}C$) films compare to $PbO_2\;and\;ZrO_2$ layers. However, as the thickness of $TiO_2$ layer increases. PZT thin films become rough and electrical characteristics were deteriorated due to remained anatase phase. On the other hand. PT interface layers result in improved morphology of PZT films and do not significantly change ferroelectric properties. It is a also observed that seed layers at the middle and top of PZT films do not give significant effects on grain size but the PT seed layer at the interface between the bottom electrode and the PZT films results in the small grain size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.50-53
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• 2009

Multi-walled carbon nanotubes (MWNTs) were synthesized on different substrates (bare Si and $SiO_2$/Si substrate) to investigate dye-sensitized solar cell (DSSC) applications as counter electrode materials. The synthesis of MWNTs samples used identical conditions of a Fe catalyst created by thermal chemical vapor deposition at $900^{\circ}C$. It was found that the diameter of the MWNTs on the Si substrate sample is approximately $5{\sim}10nm$ larger than that of a $SiO_2$/Si substrate sample. Moreover, MWNTs on a Si substrate sample were well-crystallized in terms of their Raman spectrum. In addition, the MWNTs on Si substrate sample show an enhanced redox reaction, as observed through a smaller interface resistance and faster reaction rates in the EIS spectrum. The results show that DSSCs with a MWNT counter electrode on a bare Si substrate sample demonstrate energy conversion efficiency in excess of 1.4 %.