• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.405-405
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• 2011

실리콘 질화막(SiNx : H)는 결정질 실리콘 태양전지 제작 공정에서 ARC (Anti Reflection Coating)과 표면 패시베이션의 역할로써 많이 사용되었지만, layer 자체의 quality가 좋지 않기 때문에 최근에는 SiNx/SiO2 이중 layer로 passivation layer를 형성하고 있다. SiO2 layer는 Si substrate를 소스로 하여 성장시키기 때문에 막의 질이 우수하기는 하지만, 막 성장을 위해서 Furnace를 이용해야 하기 때문에, 공정 시간과 공정 비용을 증가시키는 단점이 있다. 본 연구에서는 SiO2 layer를 Furnace가 아닌, 질산(HNO3)을 이용하여SiNx/Thin SiO2 passivation layer 제작하였다. 실험에서는 SiO2 성장을 위해서 질산 용액에 p-type wafer를 dipping하여 시간대 별, SiO2 막의 두께를 관찰하였고, passivation의 효과를 확인하기 위해 lifetime을 측정하였다. 그 결과 SiNx/SiO2 이중 passivation layer는 SiNx 단일 막으로 passivation을 하였을 때보다, lifetime이 10 us 상승했고, 셀 제작시 효율은 약 1.1%, Fill Factor는 약 4% 정도 증가한 것을 확인할 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• 센서학회지
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• 제9권5호
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• pp.389-395
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• 2000

본 논문에서는 보호용 실리콘 산화층과 Al 층을 이용한 $Al_2O_3$ 예비층의 형성을 제안하였다. 실리콘 기판 위의 보호용 산화막 위에 알루미늄을 증착하고 이를 $800^{\circ}C$에서 열처리함으로써 에피텍시 $Al_2O_3$ 예비층 형성시킬 수 있었다. 그리고 형성된 $Al_2O_3$ 예비층위에 ${\gamma}-Al_2O_3$ 층을 형성하였다. ${\gamma}-Al_2O_3$막 성장시 공정의 초기 상태에서 발생하는 $N_2O$ 가스에 의한 Si 기판의 식각을 $Al_2O_3$ 예비층을 이용함으로써 방지할 수 있었다. $Al_2O_3$ 예비층이 초박막 ${\gamma}-Al_2O_3$의 표면의 형태를 개선하는데 많은 효과가 있었다.

• 한국전기전자재료학회논문지
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• 제25권1호
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• pp.44-47
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• 2012

The $TiO_2/Si_3N_4/Ag/Si_3N_4/TiO_2$ multi layered structure was designed for the possible application of transparent electrodes in PDP (Plasma Display Panel). Multi layered film was deposited on a glass substrate at room temperature by DC/RF magnetron sputtering system and EMP (Essential Macleod Program) was adopted to optimize the optical characteristics of film. During the deposition process, the Ag layer in $TiO_2/Ag/TiO_2$ became heavily oxidized and the filter characteristic was degraded easily. In thus study, Si3N4 layer was used as a diffusion buffer layer between $TiO_2$ and Ag. in order to prevent the oxidation of Ag layer in $TiO_2/Si_3N_4/Ag/Si_3N_4/TiO_2$ structure. It was confirmed that $Si_3N_4$ layer is one of candidate materials acting as diffusin barrier between $TiO_2/Ag/TiO_2$.

• 한국표면공학회지
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• 제42권1호
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• pp.21-25
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• 2009

Using an evaporation system, $SiO_2$ was deposited as a buffer layer between a PET substrate and a ITO layer and then ITO/$SiO_2$/PET layers were annealed for 1.5 hours at the temperature of $180^{\circ}C$. Adhesion and electro-optical properties of ITO films were studied with thickness variance of a $SiO_2$ buffer layer. As a result of introduction of the $SiO_2$ buffer layer, sheet resistance and resistivity increased and a ITO film with optimum sheet resistance ($529.3{\Omega}/square$) for an upper ITO film of resistive type touch panel could be obtained when $SiO_2$ of $50{\AA}$ was deposited. And it was found that ITO films with $SiO_2$ buffer layer have higher transmittance of $88{\sim}90%$ at 550 nm wavelength than ITO films with no buffer layers and the transmittance was enhanced as $SiO_2$ thickness increased from $50{\AA}$ to $100{\AA}$. Adhesion property of ITO films with $SiO_2$ buffer layers became better than ITO films with no buffer layers and this property was independent of $SiO_2$ thickness variance ($50{\sim}100{\AA}$). By depositing a $SiO_2$ buffer layer of $50{\AA}$ on the PET substrate and sputtering a ITO thin film on the layer, a ITO film with enhanced adhesion, electro-optical properties could be obtained.

• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 대한전자공학회논문지SD
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• 제44권5호
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• pp.8-14
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• 2007

본 논문에서는 MOS 소자의 게이트 유전체로 사용될 고유전 박막으로 $HfO_2$/Hf 박막을 제조하여 그 전기적 특성을 관찰하였다. $HfO_2$박막은 TEMAH와 $O_3$ 전구체를 사용한 ALD 방법으로 p-type (100) 실리콘 웨이퍼 위에 증착하였다. $HfO_2$막을 증착시키기 전에 중간층으로써 Hf 금속 층을 증착하였다. Round-type의 MOS 커패시터 제작을 위해, 상부 전극은 Al 또는 Pt을 이용하여 약 2000 ${\AA}$ 두께의 전극을 형성하였다. $HfO_2$ 박막은 화학정량적 특성을 보였으며, $HfO_2$/Si 계면에서 Si-O 결합 대신 Hf-Si 결합과 Hf-Si-O 결합이 관찰되었다. $HfO_2$와 Si 사이의 Hf 중간층은 $SiO_x$의 성장이 억제되었고, $HfSi_xO_y$으로 변형되었다. 이러한 결과로 $HfO_2$/Hf/Si 구조에서 Hf 중간층이 있음으로 게이트 유전체의 고유전율이 유지되면서 계면 특성이 개선됨을 확인하였다.

• 한국세라믹학회지
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• 제52권4호
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• pp.290-293
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• 2015

The properties of the IZTO thin films on the glass were studied with a variation of the $SiO_2$ buffer layer thickness. $SiO_2$ buffer layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) on the glass, and the In-Zn-Tin-Oxide (IZTO) thin films were deposited on the buffer layer by RF magnetron sputtering. All the IZTO thin films with the $SiO_2$ buffer layer are shown to be amorphous. Optimum $SiO_2$ buffer layer thickness was obtained through analyzing the structural, morphological, electrical, and optical properties of the IZTO thin films. As a result, the IZTO surface roughness is 0.273 nm with a sheet resistance of $25.32{\Omega}/sq$ and the average transmittance is 82.51% in the visible region, at a $SiO_2$ buffer layer thickness of 40 nm. The result indicates that the uniformity of surface and the properties of the IZTO thin film on the glass were improved by employing the $SiO_2$ buffer layer and the IZTO thin film can be applied well to the transparent conductive oxide for display devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.418.2-418.2
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• 2016

$Al_2O_3$ passivation layer has excellent passivation properties at p-type Si surface. This $Al_2O_3$ layer forms thin $SiO_2$ layer at the interface. There were some studies about inserting thermal oxidation process to replace naturally grown oxide during $Al_2O_3$ deposition. They showed improving passivation properties. However, thermal oxidation process has disadvantage of expensive equipment and difficult control of thin layer formation. Wet chemical oxidation has advantages of low cost and easy thin oxide formation. In this study, $Al_2O_3$/$SiO_2/Si(100)$ interface was formed by wet chemical oxidation and PA-ALD process. $SiO_2$ layer at Si wafer was formed by $HCl/H_2O_2$, $H_2SO_4/H_2O_2$ and $HNO_3$, respectively. 20nm $Al_2O_3$ layer on $SiO_2/Si$ was deposited by PA-ALD. This $Al_2O_3/SiO_2/Si(100)$ interface were characterized by capacitance-voltage characteristics and quasi-steady-state photoconductance decay method.

• 한국전기전자재료학회논문지
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• 제25권1호
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.