• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.159-159
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• 2003

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1338-1342
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• 2005

We have synthesized an $Eu^{2+}$-activated $Sr_3MgSi_2O_8$ blue phosphor and $Ba_2SiO_4$ green phosphor and $Ba^{2+}$ co-doped $Sr_3SiO_5$ red phosphor investigated an attempt to develop white LEDs by combining it with a GaN blue LED $chip(\lambda_{em}=405 nm)$. Three distinct emission bands from the GaN-based LED and the $(Sr_3MgSi_2O_8:Eu\; +\; Ba_2SiO_4:Eu\; +\; Ba^{2+}\; co-doped\; Sr_3SiO_5:Eu)$ phosphor are clearly observed at 460nm, 520 nm and at around 600 nm, respectively. These three emission bands combine to give a spectrum that appears white to the naked eye. Our results show that GaN (405 nm chip)-based $(Sr_3MgSi_2O_8:Eu\; +\; Ba_2SiO_4:Eu\; +\; Ba^{2+}\; co-doped\; Sr_3SiO_5:Eu) exhibits a better luminous efficiency than that of the industrially available product InGaN (460 nm chip)-based YAG:Ce.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.155-155
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• 2012

기존의 플로팅 타입의 비휘발성 메모리 소자는 스케일 법칙에 따른 인접 셀 간의 간섭현상과 높은 동작 전압에 의한 누설전류가 증가하는 문제가 발생을 하게 된다. 이를 해결하고자 SONOS (Si/SiO2/Si3N4/SiO2/Si) 구조를 가지는 전하트랩 타입의 비휘발성 메모리 소자가 제안되었다. 하지만 터널링 베리어의 두께에 따라서 쓰기/지우기 특성은 향상이 되지만 전하 보존특성은 열화가 되는 trad-off 특성을 가지며, 또한 쓰기/지우기 반복 특성에 따라 누설전류가 증가하게 되는 현상을 보인다. 이러한 특성을 향상 시키고자 많은 연구가 진행이 되고 있으며, 특히 엔지니어드 터널베리어에 대한 연구가 주목을 받고 있다. 비휘발성 메모리에 대한 엔지니어드 기술은 각 베리어; 터널, 트랩 그리고 블로킹 층에 대해서 단일 층이 아닌 다층의 베리어를 적층을 하여 유전율, 밴드갭 그리고 두께를 고려하여 말 그대로 엔지니어링 하는 것을 뜻한다. 그 결과 보다 효과적으로 기판으로부터 전자와 홀이 트랩 층으로 주입이 되고, 동시에 다층을 적층하므로 물리적인 두께를 두껍게 형성할 수가 있고 그 결과 전하 보전 특성 또한 우수하게 된다. 본 연구는 터널링 베리어에 대한 엔지니어드 기술로써, Si3N4를 기반으로 하고 높은 유전율과 낮은 뉴설전류 특성을 보이는 ZrO2을 두 번째 층으로 하는 엔지니어드 터널베리어 메모리 소자를 제작 하여 메모리 특성을 확인 하였으며, 또한 Si3N4/ZrO2의 터널베리어의 터널링 특성과 전하 트랩특성을 온도에 따라서 특성 분석을 하였다.

• Korean Journal of Materials Research
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• v.12 no.2
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Journal of the Korean Ceramic Society
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• v.29 no.7
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• pp.511-516
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• 1992

In this study, SiC powder and Si powder were used as the raw materials. Mixture was prepared with addition of Al2O3 and Fe2O3 at 0.1~0.5wt% respectively. After this step, the mixture was pressed and nitrided for 30 hrs at 140$0^{\circ}C$ under NH3-N2 atmosphere. Mechanical properties of sintered specimens were investigated from measurement of porosity, bulk density and three point bending test. nitration reaction extent was observed at the change of mass before and after reaction, and the microstructure and the change of $\alpha$-Si3N4 and $\beta$-Si3N4 were observed by XRD and SEM. In the current work, the results are as follows 1. When Fe2O3 added, the nitridation increased with the content of Fe2O3, and the bending strength was increased from 0.1 wt% to 0.3 wt%, and decreased to 0.5 wt%. 2. When Al2O3 added, the nitridation and the bending strength increased little by little with the content of Al2O3 3. The bending strength of the specimen added with Fe2O3 were higher than that with Al2O3. Because the specimens contained Fe2O3 had much more the whisker type crystal of Si3N4 contributing to strength than contained Al2O3.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.301-307
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• 2002

Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.177-182
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• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Korean Journal of Materials Research
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• v.10 no.2
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• pp.160-165
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• 2000

We have investigated the electrical and diffusion barrier properties of MgO produced on the surface of Cu (Mg) alloy. Also the diffusion barrier property of the interfacial MgO between Cu alloy and $SiO_2$ has been examined. The results show that the $150\;{\AA}$-MgO layer on the surface remains stable up to $700^{\circ}C$, preventing the interdiffusion of C Cu and Si in Si/MgO/Cu(Mg) structure. It also has the breakdown voltage of 4.5V and leakage current density of $10^{-7}A/\textrm{cm}^2/$. In addition, the combined structure of $Si_3N4(100{\AA})/MgO(100{\AA})$ increases the breakdown voltage up to lOV and reduces the leakage current density to $8{\tiems}10^{-7}A/\textrm{cm}^2$. Furthermore, the interfacial MgO formed by the chemical reac­t tion of Mg and $SiO_2$ reduces the diffusion of copper into $SiO_2$ substrate. Consequently, Cu(Mg) alloy can be applied as a g gate electrode in TFT /LCDs, reducing the process steps.