• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.397-399
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• 2004

Generally microkernel has properties of Portability, reusability and scalability. In particular microkernel technique has been applied to development of real time kernel on embedded system because life cycle of micro processor is shortened. In this paper we study Properties of micro kernel and Comparative Performance of Nucleus and ${\mu}ITRON$ based on microkernel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1025-1031
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• 2007

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS $0.18{\mu}m$ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2136-2149
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• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.6
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• pp.894-905
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• 2004

The closed cycle diesel propulsion system is free from the problem of the intake air, exhaust gas and their control that are associated with the conventional diesel propulsion system. The system is composed of a main engine, an exhaust cooler. a $CO_2$ scrubber and a $O_2$ mixer. In this paper, a hardware using microprocessor is proposed in order to monitor and control the oxygen and ratio of specific heat for underwater diesel propulsion system. Also simulation is carried out to ascertain the performance of proposed system.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.605-610
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• 1991

In inverter system for driving induction motor, the output harmonics are hamrful in induction motor drive because it leads to ripple torque and induction interference. For electrical drives using PWM(Pulsewidth Modulation) inverters and ac motors, the methods for efficiency optimal control have been developed. In this paper, two different PWM methods for inverter and voltage control technique are described. In order to reduce or minimize losses, various forms of PWM strategy such as, PM (Positive Modulation) and NM (Negative Modulation) are discussed. The results show the feasibility of obtaining practically sinusoidal output waveforms which are highly desirable in most inverter application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.243-246
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• 2003

The design of router that converts IP packets from IPv4 network to IPv6 network using embedded Linux toolkit based on processor is presented. As an address transition platform, IPv6 module is transplanted to Linux using processor and the experiment was done with IPv4 and IPv6. In order to build the test network, it is constructed with Tunneling mechanism of IPv4 and IPv6 network. The packet value is obtained about 2$\mu$sec on average a 2 hops on the ICMP ping6.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.105-108
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• 1988

In this paper, a control system design method is proposed for DC motor drive. A state space model is used to control sysytem and for closed loop system the technique of pole assignment is applied. The control system is designed with state feedback theory and to improve the response further more feedforward theory is applied to control system. The microprocessor as a controller and the interfaces in the system are proposed. Digital simulation results for step changes in reference velocity and load torque are shown.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2374-2376
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• 1999

This paper deals with some experimental results of the ACSR inner corrosion detector which is developed in order to measure local corrosion of transmission line. Tested wire is ACSR $97{mm}^2$. Experimental procedures, desirable test results and normalizing method of corrosion grade are reported. It is shown that the detector is possible to inspect the inner corrosion of ACSR, through testing and experimental studying for artificial corroded samples.