In this paper, a fault-tolerant Mini-MAP system with high reliability is proposed. For fault-tolerance, the LLC sublayer, MAC sublayer, and physical layer of the Mini-MAP system are dualized. The detection of faults, the replacement of the failed network, and the management of the network are three major functions required for the dualization, and they are performed by ESM(Error Supervisory Machine), EMM(Error Management Machine), and NMM(Network Management Machine) of the proposed fault-tolerant Mini-MAP system, respectively. The ring maintenance function of the MAC sublayer is used for the detection of the faults. In the proposed fault-tolerant Mini-MAP system, the data are received from both of the dualized networks and transmitted to the selected one of the two. We analyze the reliability and the MTTF(Mean Time To Failure) of the proposed fault-tolerant Mini-MAP system and show that it has better performance compared to a general Mini-MAP system.

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

The process of conventional floating-point additio $n_traction operation consists of alignment, additio $n_traction, normalization, and rounding stage. Because rounding stage needs an incrementor or adder, it occupies much time and chip area. In addition, it needs additional time and hardware for renormalization which occurs in overflow due to rounding In this paper, floating-point adde $r_tractor performing rounding and additio $n_traction in parallel is presented by using the feature of additio $n_traction and carry select adder used in additio $n_tracting stage. Proposed floating point adde $r_tractor doesn't need time and incrementor nor adder for rounding. Also, renormalization doesn't occur since rounding is performed prior to normalization.to normalization.

In this paper, we propose a programmable 16 bit DSP architecture using FIFO instruction memory. With this DSP architecture, System structure, BUS structure, instruction set ant and an assembler for system test are developed. The characteristic of this structure is that it simply fetches instructions not from RAM but from FIFO using shift operations. Accordingly, System can be designed regardless of RAM access time. One cycle is enough to execute an instruction, if instruction pipeline is operated. Another merit of this structure is that we can obtain the same effect as instruction pipelining without constructing a complex pipelined controller by decreasing the pipeline number.

A new automatic cardiac output control algorithm for the motor-driven electromechanical total artificial heart(TAH) was developed based on the motor current waveform analysis without using any extra transducer. The basic control requirements of artificial heart can be described in terms of three features : preload sensitivity, afterload insensitivity, and balanced ventricular outputs. In the previous studies, many transducers were utilized to obtain informations of hemodynamic states for the automatic cardiac output control, But such automatic control systems with sensors have had reliability problems. We proposed a new sensorless automatic cardiac output control algorithm providing adequate cardiac output to the time-varying physiological demand without causing right atrial collapse, which is one of the critical problem in an active-filling type device. In-vitro tests were performed on a mock circulation system to evaluate the performance of the developed algorithm and the results show that the new algorithm satisfied the basic control requirements on the cardiac output response and the possibility of application of the developed algorithm to in vivo experiments.

This paper presents a method of implementing efficient optical flow estimation for dynamic scene analysis using the hierarchical Hopfield neural networks. Given the two consequent inages, Zhou and Chellappa suggested the Hopfield neural network for computing the optical flow. The major problem of this algorithm is that Zhou and Chellappa's network accompanies self-feedback term, which forces them to check the energy change every iteration and only to accept the case where the lower the energy level is guaranteed. This is not only undesirable but also inefficient in implementing the Hopfield network. The another problem is that this model cannot allow the exact computation of optical flow in the case that the disparities of the moving objects are large. This paper improves the Zhou and Chellapa's problems by modifying the structure of the network to satisfy the convergence condition of the Hopfield model and suggesting the hierarchical algorithm, which enables the computation of the optical flow using the hierarchical structure even in the presence of large disparities.

This paper presents a new classified vector quantization (VQ) technique using a neural network model in the transform domain. Prior to designing a codebook, the proposed approach extracts class features from a set of images using self-organizing feature map (SOFM) that has the pattern recognition characteristics and the same as VQ objective. Since we extract the class features from the training images unlike previous approaches, the reconstructed image quality is improved. Moreover, exploiting the adaptivity of the neural network model makes our approach be easily applied to designing a new vector quantizer when the processed image characteristics are changed. After the generalized BFOS algorithm allocates the given bits to each class, codebooks of each class are also generated using SOFM for the maximal reconstructed image quality. In experimental results using monochromatic images, we obtained a good visual quality in the reconstructed image. Also, PSNR is comparable to that of other classified VQ technique and is higher than that of JPEG baseline system.

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

It is assumed in the block matching algorithm(BMA) that all the pels in a block have a same motion vector. Then, the motion vector of a block in the BMA is matched to only one or none of the objects in the worst case if objects in a block have different motion vectors. This is apparent in the motion estimation using the fast BMA which has the effect of reducing the computation time and hardware complexity, compared to the full search BMA. Although the motion vector in the motion estimation using small block size is accurate, the increased number of bits is required to represent motion vectors. In this paper, new motion vector segmentation with less additional information and hardware complexity than the conventional method is proposed. In the proposed method, a motion vector is derived from the block for motion vector segmentation and another motion vector is extracted from four neighboring blocks to consiture a motion vector pair. For the accurate motion vector of each subblock, the motion vector is assigned to each subblock by mean squared error measure. And the overlapped motion compensation using window is also applied to reduce displaced frame difference.

One of the hardest problems that limit real application of production system is its slowness. One way to overcome this problem is to speed up the matching operation which occupies more than 90% of the total execution time. In this paper, we try to speed up the matching operation with parallel execution of a typical pattern matching algorithm, RETE, in a multiprocessor environment, This requires not only to make partitions of the rules but also to allocate the partitioned rules to processors, respectively. A partition strategy is proposed to make groups of similar rules by evaluating the similarity of rules according to the number of common conditions between rules. An allocation strategy is proposed to make the load of each processor even by assigning the different priority to the group of rules according to the expected amount of time required for matching operation. To compare with the existing methods, we perform simulation using OPS5 sample programs. The simulation results show that the proposed methods can improve the performance of production system.

In this paper, a Novel Approach is Proposed which Identifies linear system Parameters Using a multilayer feedforward neural network trained with backpropagation algorithm. The parameters of linear system can be represented by x9t)/x(t) and x(t)/u(t). Thud, its parameters can be represented in terms of the derivative of output with respect to input of parameters can be represented in terms of the derivative of output with respect to input of trained neural network which is a function of weights and output of neurons. Mathematical representation of the proposed approach is derived, and its validity is shown by simulation results on 2-layer and 3-layer neural network.

A batch-mode algorithm is proposed to increase the speed of learning in the error backpropagation algorithm with variable learning rate and variable momentum parameters in classification problems. The objective function is normalized with respect to the number of patterns and output nodes. Also the gradient of the objective function is normalized in updating the connection weights to increase the effect of its backpropagated error. The learning rate and momentum parameters are determined from a function of the gradient norm and the number of weights. The learning rate depends on the square rott of the gradient norm while the momentum parameters depend on the gradient norm. In the two typical classification problems, simulation results demonstrate the effectiveness of the proposed algorithm.

Multilayer neural networks with backpropagation learning algorithm are widely used for pattern classification problems. For many real applications, it is more important to reduce the misclassification rate than to increase the rate of successful classification. But multilayer perceptrons(MLP's) have drawbacks of slow learning speed and false convergence to local minima. In this paper, we propose a new method for character recognition problems with a single-layer network and double rejection mechanisms, which guarantees a very low misclassification rate. Comparing to the MLP's, it yields fast learning and requires a simple hardware architecture. We also introduce a new coding scheme to reduce the misclassification rate. We have prepared two databases: one with 135,000 digit patterns and the other with 117,000 letter patterns, and have applied the proposed method for printed character recognition, which shows that the method reduces the misclassification rate significantly without sacrificing the correct recognition rate.