In this paper, to realize the network management function in automated manufacturing network Mini-MAP, the network management requirements are analyzed and the network management system is implemented on the basis of this analysis. The implemented management system which has both local management and remote management mechanism is considered as a single domain on the Mini-MAP network. Here, the remote management functions consist of network status, monitoring and remote operations and the local management functions have parameter display and network self testing. The MAP network controller is designed according to the MAP version 3.0 specifications and IEEE 802 standards. the operations of network management system are certified througth the test environments which consists of the implemented network adaptor and softwares for Mini-MAP.

In this paper, CCF(Call Control Function), functional entity for basic call processing in SSP(Service Switching Point), is designed and implemented. This functional entity can provide the IN(Intelligent Network) services which are included in CCITT CS-1(Capability Set-1), near-term process for IN Architecture. UIO(Unique Input Output) method, one of the thest sequence generation methods for the finite state machine, is used for the implementation test of this functional entity.

In this paper, the concept of sampling vectors is introduced, and used for a simple realization of DSSs(distributed sample scramblers). In DSSs, if the sampling times of the scrambler state samples are not identical to their transmission times, samples are delayedtransmitted to the descrambler. and in this case the DSSs need additional memory elements storing the samples and additional clocks for informing their transmission times. The concept of sampling vectors helps move the sampling times of delayed samples to their transmission times, thus eliminating the additional memory elements and clocks in the DSSs. In the paper, the conditions on the synchronization of the scrambler and descrambler are derived for the DSS employing sampling vectors,and demonstrations are given on their applicaitons to cell-based ATM DSSs.

The MESFET can be used as a three-terminal varactor by employing gate depletion capacitance Cg. In this paper, a novel VCDRO(voltage controlled dielecric resonator oscillator) is designed to apply VCDRO with this concept. The VCDRO produced 6.33dBm output power at a frequency of 11.058GHz and tunning bandwidth of 45MHz. The advantage of using the MESFET as a three-terminal varactor is to let the MESFET play both roles at the same time, thus simplifying the circuit configuration and fabrication. This finding demonstrates the potential of using both real and imaginary parts of the equivalent impedance of the active device.

By the variational method, the coplanar waveguide(C.P.W) shielded by two conducting plates has been analyzed. The particular potential solution has been obtained for the boundary conditions in C.P.W. The characteristic impedance and the effective dielectric constant in C.P.W. have been obtained by the variational method using the potential function and the assumed basis function for charge distributions. To consider the effect of the conducting plate in C.P.W. two cases, with and without the top plate, have been analyzed and compared respectively.

Three-dimensional simulator for the ion implantation process is developed. The simulator based on an analytical model which would be a choice with high computational efficiency and accuracy. This is an important issue for the simulation of a numerous number of processing steps required in the fabrication of ULSI or GSI. The model can explain scattering and bulk channeling mechanism (1D). It can also explain depth dependent lateral diffusion effect(2D) and mask effect(3D). The model is consist of one-dimensional JPD(Joined Pearson Distribution) function and two-dimensional modified Gaussian functions. Final implanted profiles under typical mask structures such as hole, line and island structure are obtained with varying ion species.

A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

The statistical methodology using RSM (response surface method) was used too ptimize the deposition conditions of selective CVD tungsten process for improving the deposition rate and the adhesion property. Temperature, flow rate of SiH$_4$ and WF$_6$ and H$_2$ and Ar carrier gases were chosen for the deposition variables and process characteristics due to carrier gas were intensively investigated. It was observed that temperature was the main factor influencingthe deposition rate in the case of H$_2$ carrier gas while the reactant ratio, $SiH_{4}/WF_{6}$, had the principal effect on the deposition rate in the case of Ar carrier gas. The increased deposition rate and the good adhesion to Si were obtained under Ar carrier gas compared to H$_2$ carrier gas. The optimum conditions for deposition rate and antipeeling property were found to be the temperature range of 300~32$0^{\circ}C$ and the reactant ratio, $SiH_{4}/WF_{6}$, of 0.5~0.6.

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

When realizing a multiple-output function by a PLA, there is often the flexibility to choose either uncomplementary or complementary phase for each output. In this case, it is possible to significantly reduce the number of product terms by fully exploiting the freedom. This paper presents a PLA phase for each output of a multiple-output function so that the product terms for each output are maximally shared with the other outputs. and then minimizes the multiple-output function with the assigned output phase assignment. The algorithm has been implemented on Sun4/330 in C language and compared with the previous approaches for 56 example PLA`s. The proposed algorithm has obtained better results for 18-32 PLA's, worse results for 1-5 PLA`s, and the same results for 23-33 PLA's. Moreover, the computation time is much less than for the previous approaches.

In this paper we propose a new thchnology mapping algorithm for multiplexer-based FPGA's The algorithm consists of three phases` First, it converts the logic functions and the basic logic mocule into BDD's. Second. it covers the logic function with the basic logic modules. Lastly, it reduces the number of basic logic modules used to implement the logic function after going through cell merging procedure. The binate selection is employed to determine the order of input variables of the logic function to constructs the balanced BDD with low level. That enables us to constructs the circuit that has small size and delay time. Technology mapping algorithm of previous work used one basic logic module to implement a two-input or three-input function in logic functions. The algorithm proposed here merges almost all pairs of two-input and three-input functions that occupy one basic logic module. and improves the mapping results. We show the effectiveness of the algorithm by comparing the results of our experiments with those of previous systems.

This paper describes the design and implementation of a CAD object management system for the design library in VHDL design environment. For the efficient manipulation of design objects, the library is managed independently of the underlaid CAD system. Management and revision of design objects can be performed by a batch script of server commands or through the user interaction in the X/MOTIF graphic environment. Through the library server, design management tasks can be efficiently performed, such as configuration of design objects, version control, and management of attributes and methods for versions. Experimental results show that the proposed system is a viable tool for the management of design data in VHDL design environment.

A ner general multi-layer area router, called DINOSAUR, is presented in this paper. DINOSAUR can route various types of routing areas, such as L-shaped channel, switchbox with/without obstacles, and rectilinear area with/without internal modules/terminals. The DINOSAUR algorithm consists of three major stages: layerless maze routing, layering by coloring, and rip-up and reroute. In layerless maze roution stage, the route of each net is determined by modified maze algorithm without taking the conflicts(short. circuits) into account. In layering by coloring stage, the layer of each net is determinde by a heuristic coloring algorithm. When the conflicts are not removed, rip-up and reroute process is invoded. In rip-up and reroute stage, the conflicts are removed iteratively. Many test cases have been run, and on all the benchmark data known in the literature DINOSAUR has performed either better than or comparable to the other routers.