전기전자학회논문지 (Journal of IKEEE)

  • 제28권3호
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  • Pages.369-374
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  • 2024
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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트랜지스터의 온도 계수를 고려한 커패시터리스 디램의 설계 최적화

Design Optimization of Capacitor-less DRAM using zero-temperature coefficient point

  • 김경희 ;
  • 김경민 ;
  • 김영환 ;
  • 임종범 ;
  • 최규호 ;
  • 강인만 ;
  • 윤영준
  • Kyung Hee Kim (Department of Electronic Engineering, Andong National University) ;
  • Kyeong Min Kim (Department of Electronic Engineering, Andong National University) ;
  • Yeong Hwan Kim (Department of Electronic Engineering, Andong National University) ;
  • Jong Beom Im (Department of Electronic Engineering, Andong National University) ;
  • Gyu Ho Choi (Department of Electronic Engineering, Andong National University) ;
  • In Man Kang (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Young Jun Yoon (Department of Electronic Engineering, Andong National University)
  • 투고 : 2024.09.13
  • 심사 : 2024.09.24
  • 발행 : 2024.09.30
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초록

본 논문에서는 차세대 메모리 기술로 주목받고 있는 커패시터리스 디램(one-transistor DRAM, 1T-DRAM)을 소자의 설계 최적화에 대해 다룬다. 기존 커패시터기반 DRAM의 한계를 해결하고자, 비대칭 듀얼 게이트 구조를 사용하여 보유 시간 및 성능을 향상시키는 방향성을 제시한다. ZTC(Zero-temperature coefficient) 지점을 1.25 V로 설정하여 온도 변화에 따른 성능 저하를 최소화하였다. 다양한 온도(300K~400K)에서 전류-전압 특성을 분석하여, ZTC 지점에서의 메모리 특성이 온도에 안정적으로 동작하는 것을 확인하였으며, 고온에서도 신뢰성 있는 동작을 보장하는 설계가 가능함을 입증하였다. 이를 통해 1T-DRAM 소자는 높은 신뢰성과 고효율을 갖춘 메모리 기술로서, 차세대 메모리 소자 개발에 중요한 기여를 할 수 있다.

This paper addresses the design optimization of capacitorless DRAM(one-transistor DRAM., 1T-DRAM), which has gained attention as a next-generation memory technology. To overcome the limitations of conventional capacitor-based DRAM, an asymmetric dual-gate structure is proposed to enhance retention time and overall performance. The zero-temperature coefficient (ZTC) point is set at 1.25 V to minimize performance degradation due to temperature variations. Current-voltage characteristics were analyzed at various temperatures (300K-400K), confirming stable memory operation at the ZTC point, even under temperature fluctuations. The proposed design demonstrates reliable operation at high temperatures, proving the potential for high-efficiency, highly reliable memory technology. As a result, the 1T-DRAM device can make a significant contribution to the development of next-generation memory devices.

키워드

과제정보

This work was supported by a grant from 2024 Research Fund of Andong National University.

참고문헌

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