Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

A Study on Self-bias SCR Based on LRSCR for Low Voltage Class ESD Protection

저전압급 ESD 보호를 위한 LRSCR 기반 Self-bias SCR에 관한 연구

  • U-Yeol Seo (Dept. of Electronics Engineering, Dankook University) ;
  • Sang-wook Kwon (Dept. of Electronics Engineering, Dankook University) ;
  • Jae-yoon Oh (Dept. of Electronics Engineering, Dankook University) ;
  • Yong-Seo Koo (Dept. of Electronics Engineering, Dankook University)
  • 서우열 ;
  • 권상욱 ;
  • 오재윤 ;
  • 구용서
  • Received : 2024.06.10
  • Accepted : 2024.06.24
  • Published : 2024.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposed an ESD protection device that improved the current driving ability through Self-bias than the existing ESD protection device. The new proposed structure is based on the LRSCR structure and adds an N+ diffusion region, and reduces resistance by connecting the gate and the P+ diffusion region. As a result, it was confirmed that the proposed ESD protection device exhibits a trigger voltage of 11.8V and a holding voltage of 5.9V. It can be used in 5V applications for low voltage and is expected to have excellent current driving capability.

본 논문에서는 기존의 ESD 보호소자보다 Self-bias를 통하여 전류구동 능력을 향상시킨 ESD 보호소자를 제안하였다. 새로운 제안 구조는 LRSCR구조 기반이며 N+ 확산 영역을 추가하였으며 게이트와 P+ 확산영역을 연결하여 저항을 감소시킨다. 그 결과, 제안된 ESD 보호소자는 11.8V의 트리거 전압과 5.9V의 홀딩 전압을 나타내는 것으로 확인되었다. 저전압용 5V 애플리케이션에 사용될 수 있으며 우수한 전류구동능력을 가지고있을 것으로 기대된다.

Keywords

Acknowledgement

This paper was supported by Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korea Government(MOTIE)(RS-2024-00403586, Development of Reinforced Insulated High Reliability Integrated Power IC Technology including Digital Precision Control) and conducted with the support of the Compound Material-based Next Generation Power Semiconductor Technology Development Project of the Ministry of Trade, Industry and Energy and the Korea Institute for Industrial Technology Evaluation (RS-2022-00143842, "Single/Three-phase AC/DC Converter Smart Power IC using SiC MOSFET devices")

References

  1. M. Ker and C. Yen, "Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test," IEEE J. Solid-State Circuits, vol 43, no. 11, pp.2533-2545, 2008. DOI: 10.1109/JSSC.2008.2005451
  2. Y. Koo, K. Lee, K. Kim, and J. Kwon, "Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology," J. Microelectron, vol.40, no.6, pp.1007-1012, 2009. DOI: 10.1016/j.mejo.2009.01.001
  3. C. Lin and R. Chang, "Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process," IEEE Trans. Electron Devices, vol. 62, no.9, pp.2824-2829, 2015. DOI: 10.1109/TED.2015.2450225
  4. O. Semenov, H. Sarbishaei, and M. Sachdev, "ESD protection design for advanced CMOS," in Proc. SPIE, pp.123-131, 2001.
  5. B. Song, K. Do, Y. koo, "SCR-Based ESD Protection Using a Penta-Well for 5V Applications," IEEE Journal of the Electron Devices Society, vol. 6, pp.691-695, 2018. DOI: 10.1109/JEDS.2018.2817636
  6. O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," in Proc. EOS/ESD Symp., pp.77-86. 2006.