Acknowledgement
This work was supported by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) P0020966. This work was also supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2022M3I8A107243). The EDA tools were supported by IDEC.
References
- D. Park, J. Kim, "A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL," Circuits Syst Signal Process 39, 1715-1734, 2020. DOI: 10.1109/ISCAS.2018.8351396
- F. -W. Kuo et al., "An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs," IEEE Transactions on Circuits and Systems I, vol.65, no.11, pp.3756-3768, 2018. DOI: 10.1109/TCSI.2018.2855972
- J. Yu, F. F. Dai and R. C. Jaeger, "A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 ㎛ CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 45, no.4, pp.830-842, 2010. DOI: 10.1109/JSSC.2010.2040306
- J. Jin, S. Kim and J. Kim, "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems," IEEE Access, vol.10, pp.124217-124226, 2022. DOI: 10.1109/ACCESS.2022.3224451
- D. Park, S. Choi, and J. Kim, "A fast lock all-digital MDLL using a cyclic Vernier TDC for burst-mode links," Electronics, vol.10, no.2, p.177, 2021. DOI: 10.3390/electronics10020177
- Avilala, Akhil, et al, "High Resolution Time-to-Digital Converter Design with Anti-PVT-Variation Mechanism," 2021 IEEE 4th International Conference on Electronics Technology (ICET), pp.452-455, 2021. DOI: 10.1109/ICET51757.2021.9451146
- Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, and Ponnan Suresh, "Anti-PVT-Variation Low Power Time-to-Digital Converter Design Using 90nm CMOS Process," IEEE Transactions on Very Large Scale integration (TVLSI) Systems, vol.28, no.9, pp.2069-2073, 2000. DOI: 10.1109/TVLSI.2020.3008424