• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.119-125
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• 2014

In this paper, we developed the signal generator of GNSS navigation signals and analysis the performance of DCO(Digitally Clock Oscillator) compensation algorithm for cumulative distance error thorough simulation. In general, To generate a GNSS signal calculates the Doppler and Initial Pseudorange by using the location information of the receiver and the satellite. The GNSS signal generator generates a signal by determine the carrier and code output frequency using the Doppler information which is calculated as a function of time. The output frequency of the carrier and code would be used the DCO scheme. At this time, It extract the bit and code information on a for each sample by accumulating the DCO. an error of Pseudorange is generated by the cumulative error of the DCO. If Pseudorange error occurs, so that the influence to and operation of the receiver. Therefore, in this paper, we implemented the accumulated error compensation algorithm of the DCO to remove the accumulated error components DCO thereof, Pseudorange accumulated error is removed through the experiment, it was confirmed to be a high accuracy can be operated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.106-111
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• 2000

In this paper, we designed the DCO controller of frequency synthesizer by combing the m DS, DDS, and PLL methods to improve the performances(transition time, stability, re Designed DCO controller used parallel processing and pattern matching techniques. The designed DCO controller in this thesis profits the rapid and exact synchronization wh handed off in the mobile communication.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.850-853
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• 2011

HPA(Host Protected Area) 영역과 DCO(Device Configuration Overlay) 영역은 사용자가 일반적으로 접근할 수 없는 영역이며 이 위치에 데이터를 저장하거나 은닉할 수 있다. HPA/DCO 영역은 저장 장치와의 통신을 위해 만들어진 규약인 ATA-4와 ATA-6에서 제시되었다. 디지털 포렌식 조사시 HPA/DCO 영역을 고려하지 않은 디스크 이미징 및 데이터 추출 방법은 해당 영역에 숨겨진 유용한 정보를 획득할 수 없다. 따라서 디지털 포렌식 관점에서 HPA/DCO 영역은 중요한 의미를 가지고 있으며, 해당 영역에 존재하는 데이터를 인식하여 획득하는 절차를 통해 디스크 이미징 또는 데이터 추출이 이루어져야 한다. 본 논문은 HPA/DCO 영역에 관한 기존 연구를 활용하여 포렌식 조사에서 해당 영역을 확인하고 접근할 수 있는 방법을 제시하며, HPA/DCO 영역에 저장되어 있는 데이터를 획득하여 디지털 포렌식 조사시 활용할 수 있도록 한다.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• ETRI Journal
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• v.33 no.2
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• pp.201-209
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• 2011

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of IKEEE
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• v.27 no.4
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• pp.573-578
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• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.