DOI QR코드

DOI QR Code

Vertical PIP 커패시터를 이용한 MTP 메모리 IP 설계

Design of MTP memory IP using vertical PIP capacitor

  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University) ;
  • Cha, Jae-Han (SK hynix system ic INC.) ;
  • Jin, Hongzhou (Department of Electronic Engineering, Changwon National University) ;
  • Lee, Do-Gyu (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University) ;
  • Park, Mu-Hun (Department of Electronic Engineering, Changwon National University)
  • 투고 : 2020.01.03
  • 심사 : 2020.02.17
  • 발행 : 2020.02.28

초록

Wireless charger, USB type-C 등의 응용에서 사용되는 MCU는 추가 공정 마스크가 작으면서 셀 사이즈가 작은 MTP 메모리가 요구된다. 기존의 double poly EEPROM 셀은 사이즈가 작지만 3~5 장 정도의 추가 공정 마스크가 요구되고, FN 터널링 방식의 single poly EEPROM 셀은 셀 사이즈가 큰 단점이 있다. 본 논문에서는 vertical PIP 커패시터를 사용한 110nm MTP 셀을 제안하였다. 제안된 MTP 셀의 erase 동작은 FG와 EG 사이의 FN 터널링을 이용하였고 프로그램 동작은 CHEI 주입 방식을 사용하므로 MTP 셀 어레이의 PW을 공유하여 MTP 셀 사이즈를 1.09㎛2으로 줄였다. 한편 USB type-C 등의 응용에서 요구되는 MTP 메모리 IP는 2.5V ~ 5.5V의 넓은 전압 범위에서 동작하는 것이 필요하다. 그런데 VPP 전하펌프의 펌핑 전류는 VCC 전압이 최소인 2.5V일 때 가장 낮은 반면, 리플전압은 VCC 전압이 5.5V일 때 크게 나타난다. 그래서 본 논문에서는 VCC detector 회로를 사용하여 ON되는 전하펌프의 개수를 제어하여 VCC가 높아지더라도 펌핑 전류를 최대 474.6㎂로 억제하므로 SPICE 모의실험을 통해 VPP 리플 전압을 0.19V 이내로 줄였다.

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

키워드

참고문헌

  1. F. Xu, X. Q. He, L. Zhang, "Key Design Techniques of A 40ns 16K Bits Embedded EEPROM Memory", 2004 International Conference on Communications, Circuits and Systems, vol. 2, pp. 1516-1520, June 2004.
  2. A. Conte, G. L. Gudiceo, G. Palumbo, A. Signorello, "A High-Performance Very Low-Voltage Current Sense Amplifier for Nonvolatile Memory", IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 507-514, Feb. 2005. https://doi.org/10.1109/JSSC.2004.840985
  3. H. Hidaka, "Embedded Flash Memory for Embedded Systems: Technology, Deign for Sub-systems, and Innovations," Springer International Publishing, 2017.
  4. M. Hatanaka et al., "Value Creation in SOC/MCU Applications by Embedded Non-Volatile Memory Evolutions," Asian Solid State Circuits Conference, pp. 38-42, Nov. 2007.
  5. G. S. Cho, et al., "Design of a Small-Area Low-Power, and High-Speed 128-KBit EEPROM IP for Touch Screen Controllers," Journal of KIIC, vol. 13, no. 12, pp. 2633-2640, Dec. 2009.
  6. Heon Park et al., "Design of a Cell Verification Module for Large-Density EEPROMs," JKIIECT, vol. 10, no. 2, pp. 176-183, Oct. 2017.
  7. Y. H. Kim et al., "Design of an Embedded Flash IP for USB Type-C Applications," JKIIECT, vol. 12, no. 3, pp. 312-320, June 2019.
  8. Y. H. Kim et al., "Design of 40ns 512Kb EEPROM IP," Proceedings of the 4th ICIECT 2018, pp. 245-246, July 2018.
  9. Y. H. Kim et al.,"Study on Memory Circuit Structure Analysis," ETRI Report, Oct. 2017.
  10. Y. K Ha et al., "Design of Zero-Layer FTP Memory IP," JKIIEC , vol. 11, no. 6, pp. 742-750, Dec. 2018.
  11. Chih-Ping, Chung and Kuei-Shu Chang-Liao. "A highly scalable single poly-silicon embedded electrically erasable programmable read only memory with tungsten control gate by full CMOS process." IEEE Electron Device Letters, vol. 36, no. 4, pp. 336-338, Feb. 2015. https://doi.org/10.1109/LED.2015.2404854
  12. Y. Roizin et al., "High density MTP logic NVM for power management applications," IEEE International memory workshop, pp. 1-2, June 2009.
  13. J. S. Hu et al., "A DC-DC Converter IP Design using a Multi-Phase Charge Pumping Scheme," ITC-CSCC, pp. 539-542, 2004.
  14. P, Favrat, "A High-Efficiency CMOS Voltage Doubler", IEEE JSSC, vol. 33, no. 3, pp. 410-416, Mar. 1998.
  15. G. H. Lim et. al., "Charge pump design for TFT-LCD driver IC using stack-MIM capacitor," IEICE Trans on Electronics, vol. E91-C, no. 6, pp. 928-935, June 2008. https://doi.org/10.1093/ietele/e91-c.6.928