DOI QR코드

DOI QR Code

기준 전압 발생기와 연속 시간 선형 등화기를 가진 6 Gbps 단일 종단 수신기

6-Gbps Single-ended Receiver with Continuous-time Linear Equalizer and Self-reference Generator

  • 이필호 (금오공과대학교 전자공학부) ;
  • 장영찬 (금오공과대학교 전자공학부)
  • Lee, Pil-Ho (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Jang, Young-Chan (School of Electronic Engineering, Kumoh National Institute of Technology)
  • 투고 : 2016.06.16
  • 심사 : 2016.08.31
  • 발행 : 2016.09.25

초록

본 논문에서는 6 Gbps 고속 double data rate(DDR) 인터페이스를 위한 기준 전압 발생기와 선형 등화기를 포함하는 단일 종단 수신기를 제안한다. 제안하는 단일 종단 수신기는 낮은 전압 레벨의 입력 신호에 대해 전압 이득을 증가시키기 위해 공통 게이트 증폭기를 사용한다. 저주파의 이득을 줄이고 고주파 피킹 이득을 발생시키는 연속 시간 선형 등화기가 공통 게이트 증폭기에서의 구현을 위해 제안된다. 또한, 공통 게이트 증폭기의 오프셋 노이즈를 줄임으로 전압이득을 극대화하기 위해 기준 전압 발생기가 구현된다. 제안하는 기준 전압 발생기는 디지털 평준화 기법에 의해 2.1 mV의 해상도로 제어된다. 제안된 단일 종단 수신기는 공급전압 1.2 V의 65 nm CMOS 공정에서 설계되었으며 6 Gbps의 동작속도에서 15 mW의 전력을 소모한다. 설계된 등화기는 저주파에서의 이득 대비 3 GHz 주파수에서의 피킹 이득을 5 dB 이상 증가시킨다.

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

키워드

참고문헌

  1. T. C. Hsueh et al., "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 444-445, Feb. 2014.
  2. H. W. Park et al., "Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels," Journal of Semiconductor Technology and Science, vol. 16, no. 1, pp. 112-117, Feb. 2016. https://doi.org/10.5573/JSTS.2016.16.1.112
  3. S. J. Bae et al., "A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a Programmable DQ Ordering Crosstalk Equalizer and Adjustable Clock-Tracking BW," in IEEE ISSCC Dig. Tech. Papers, pp. 498-500, Feb. 2011.
  4. A. Amirkhany et al., "A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface," IEEE JSSC, vol. 47, no. 4, pp. 911-925, Apr. 2012.
  5. S. J. Bae et al., "A 40nm 7Gbps/pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface," in Proc. IEEE Symp. VLSI, pp. 193-194, 2010.
  6. H. Lee et al., "A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel," IEEE JSSC, vol. 50, no. 11, pp. 2613-2624, Nov. 2015.
  7. Y. C. Cho et al., "A Sub-1.0V 20nm 5Gb/s/pin Post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and Adaptive Calibration Scheme For Mobile Application," in Proc. IEEE Symp. VLSI, pp. 240-241, 2013.
  8. M. Bucher et al., "A 6.4-Gbps Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems," IEEE JSSC, vol. 49, no. 1, pp. 127-139, Jan. 2014.
  9. K. Kaviani et al., "A 0.4-mW/Gbps Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gbps Source-Series Terminated Transceiver," IEEE JSSC, vol. 48, no. 3, pp. 636-648, Mar. 2013.
  10. J. H. Ku et al., "A 13-Gbps Low-swing Low-power Near-ground Signaling Transceiver," Journal of The Institute of Electronics and Information Engineers, vol. 51, no. 4, pp. 49-58, Apr. 2014. https://doi.org/10.5573/ieie.2014.51.4.049
  11. J. M. Kang et al., "A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation," Journal of Institute of Electronics Engineers of Korea, vol. 50, no. 12, pp. 71-79, Dec. 2013.
  12. M. Miyahara et al., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," in Proc. IEEE A-SSCC, pp. 269-272, Nov. 2008.
  13. Y. J. Chen et al., "A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS," IEEE JSSC, vol. 51, no. 2, pp. 357-364, Feb. 2016.
  14. Y. Zhu et al., "An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS," IEEE JSSC, vol. 51, no. 5, pp. 1223-1234, May. 2016.
  15. W. S. Choi et al., "A 0.45-to-0.7V 1-to-6Gbps 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS," in IEEE ISSCC Dig. Tech. Papers, pp. 66-68, Feb. 2015.
  16. Y. S. Kim et al., "A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL," IEEE JSSC, vol. 46, no. 2, pp. 435-444, Feb. 2011.