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A Study on RF Large-Signal Model for High Resistivity SOI MOS Varactor

High Resistivity SOI MOS 버랙터를 위한 RF 대신호 모델 연구

  • Hong, Seoyoung (Department of Electronics Engineering, Hankuk University of Foreign Studies) ;
  • Lee, Seonghearn (Department of Electronics Engineering, Hankuk University of Foreign Studies)
  • 홍서영 (한국외국어대학교 전자공학과) ;
  • 이성현 (한국외국어대학교 전자공학과)
  • Received : 2016.02.03
  • Accepted : 2016.08.31
  • Published : 2016.09.25

Abstract

A new large-signal model including the voltage-dependent extrinsic gate capacitance for RF channel distribution effect is developed for a high resistivity(HR) silicon-on-insulator(SOI) RF accumulation-mode MOS varactor. The data of voltage-dependent parameters are extracted by using accurate S-parameter optimization, and empirical model equations are constructed by data fitting process. The RF accuracy of this new model is validated by observing excellent agreements between modeled and measured Y11-parameter data in the wide voltage range up to 20 GHz.

RF 채널 분포효과를 위한 전압 종속 외부 게이트 커패시턴스가 사용된 High resistivity(HR) silicon-on-insulator(SOI) RF accumulation-mode MOS 버랙터의 대신호 모델이 새롭게 개발되었다. 이 모델의 전압 종속 파라미터들은 정확한 S-파라미터 optimization을 사용하여 추출되었고, 이를 피팅하여 empirical 모델 방정식을 구축하였다. 이러한 새로운 대신호 RF 모델은 넓은 전압영역에서 측정된 Y11-파라미터 데이터와 20 GHz까지 잘 일치함으로써 정확도가 검증되었다.

Keywords

References

  1. P. Andreani and S. Mattisson, "On the use of MOS varactors in RF VCOs," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000. https://doi.org/10.1109/4.845194
  2. N. Fong, J. Kim, J.-O. Plouchart, N. Zamdmer, D. Liu, L. Wagner, C. Plett, and G. Tarr, "A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 841-846, 2004. https://doi.org/10.1109/JSSC.2004.826341
  3. M.-C. Park, S.-H. Jung, and Y.-S. Eo, "$0.13{\mu}m$ CMOS Quadrature VCO for X-band Application" Journal of The Institute of Electronic Engineers of Korea-SD vol. 49, no. 8, pp. 41-46, 2012.
  4. K. Benaissa, J.-Y. Yang, D. Crenshaw, B. Williams, S. Sridhar, J. Ai, G. Boselli, S. Zhao, S. Tang, S. Ashburn, P. Madhani, T. Blythe, N. Mahalingam, and H. Shichijo, "RF CMOS on High-Resistivity Substrates for System-on-Chip Applications," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 567-576, Mar. 2003. https://doi.org/10.1109/TED.2003.810470
  5. K. B. Ali, C. R. Neve, A. Gharsallah, and J.-P. Raskin, "RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate," IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 722-728, 2014. https://doi.org/10.1109/TED.2014.2302685
  6. J. Ahn and S. Lee, "A Study on Improved Optimization Method for Modeling High Resistivity SOI RF CMOS Symmetric Inductor," Journal of The Institute of Electronics and Information Engineers, vol. 52, no. 9, pp. 21-27, 2015. https://doi.org/10.5573/ieie.2015.52.9.021
  7. S. S. Song and H. Shin, "A New RF Model for the Accumulation-Mode MOS Varactor," IEEE MTT-S Int. Microwave Symp. Dig., pp. 1023-1026, 2003.