마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제23권4호
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  • Pages.25-29
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  • 2016
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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5 nm 급 반도체 배선 공정 기술 개발

Development of Interconnect Process Technology for 5 nm Technology Nodes

  • Choi, Eunmi (Department of Nano materials Science & Engineering, School of Integrative Engineering, Chung-Ang University) ;
  • Pyo, Sung Gyu (Department of Nano materials Science & Engineering, School of Integrative Engineering, Chung-Ang University)
  • 투고 : 2016.12.12
  • 심사 : 2016.12.17
  • 발행 : 2016.12.31
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초록

The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.

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