Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Low-Cost CRC Scheme by Using DBI(Data Bus Inversion) for High Speed Semiconductor Memory

고속반도체 메모리를 위한 DBI(Data Bus Inversion)를 이용한 저비용 CRC(Cyclic Redundancy Check)방식

  • Received : 2015.06.29
  • Accepted : 2015.08.05
  • Published : 2015.09.30
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Abstract

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

고속동작을 위한 반도체 메모리 제품에서 데이터의 신뢰도를 개선하기 위해 CRC(Cyclic Redundancy Check) 기능이 내장되었으며, 데이터전송 속도 개선을 위해 DBI(Data Bus Inversion) 기능이 내장되었다. DDR4, GDDR4 등의 제품에 추가된 기존의 ATM-8 HEC 코드 방식은 부가회로 면적이 크고(~XOR 700 gates) CRC 처리 시간이 길어서(XOR 6단), 저전력 메모리 제품의 데이터 읽기, 쓰기시 내부 동작 마진(margin)에 적지 않은 부담을 초래한다. 본 논문에서는 저비용, 고속 반도체 메모리에 적합한 CRC방식을 제안하였으며 92%의 부가회로가 개선되었다. 제안한 CRC방식의 저비용 구현을 위해 DBI 기능을 이용하여 데이터 비트 오류 검출율을 보완하였으며, 오류 검출율을 분석하여 기존의 CRC방식과 비교하였다.

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References

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