• Aerospace Engineering and Technology
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• v.13 no.2
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• pp.38-46
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• 2014

CRC (Cyclic Redundancy Codes) is a error detection method for the date transmission, which is applied to the GRDDP (GOES-R Reliable Data Delivery Protocol) between satellite and GEMS (Geostationary Environmental Monitoring Sensor) on the GEO-KOMPSAT 2B development. This paper introduces a principle of the table based CRC, and explains software implementation results of the CRC8 applied to GEMS.

• Journal of the Korean Society of Radiology
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• v.12 no.5
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• pp.575-582
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• 2018

This article compared accuracy of 5 types of radionuclide activity meters that are being used in medical institutions and proposed the correction factor for each radionuclide activity meters type, using Ge-68/Ga-68 radiation sources for scanner setting, regular scanner correction, attenuation correction, and normalization. The calibration constant between baseline values and measured values by CRC-15R, CRC-15 PET, CRC-712M, CRC-15 Beta, and CRC-25PET was 0.99999(P<0.0001), which showed very high linearity. In the accuracy test, CRC-15R, CRC-15 PET, CRC-712M, CRC-15 Beta, and CRC-25PET model showed -3.232%, -1.342%, -2.815%, -2.913%, and -3.089% respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.438-449
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• 2012

This paper presents new CRC-p codes for VHF band maritime wireless communication system based on performance analysis of various CRC codes. For this purpose, we firstly describe the method of determination of undetected error probability and minimum Hamming distance according to variation of CRC codeword length. By using the fact that the dual code of cyclic Hamming code and primitive BCH code become maximum length codes, we present an algorithm for computation of undetected error probability and minimum Hamming distance where the concept of simple hardware that is consisted of linear feedback shift register is utilized to compute the weight distribution of CRC codes. We also present construction of transmit data frame of VHF band maritime wireless communication system and specification of major communication parameters. Finally, new optimal CRC-p codes are presented based on the simulation results of undetected error probability and minimum Hamming distance using the various generator polynomials of CRC codes, and their performances are evaluated with simulation results of bit error rate based on the Rician maritime channel model and ${\pi}$/4-DQPSK modulator.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.6 s.312
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• pp.40-47
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• 2006

This paper introduces an efficient CRC logic partitioning algorithm to design pipelined parallel CRC circuits aimed at improving speed performance. Focusing on the cases that the input data width is greater than the polynomial degree, equations are derived to divide the parallel CRC logic and decide the length of the pipeline stage. Through design experiments on different types of parallel CRC circuits, we have found a significant reduction in delay by adopting our approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.590-603
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• 1989

In tnis paper, the CRC-CCITT code and primitive polynomial CRC code are selected for analysing error detecting performance. However, general formulas for obtaining the weight distribution of these two CRC codes are not so far dericed. So, a new method for calculating the weight distribution of the shortened cyclic Hamming code is presented and an undetected error probability of these two codes is obtained when used in cell of ATM for broadband ISDN user-network interface. Consequently, we show that CRC code too much does affect its error detection performance. All the computer simulation is performed by IBM PC/AT.

• Asian Pacific Journal of Cancer Prevention
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• v.16 no.2
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• pp.667-674
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• 2015

Background: Colorectal cancer (CRC) is the third most common malignancy in Malaysia, where data are limited regarding knowledge and barriers in regard to CRC and screening tests. The aim of the study was to assess these parameters among Malaysians. Materials and Methods: The questionnaires were distributed in the Umra Private Hospital in Selangor. The questionnaire had four parts and covered social-demographic questions, respondent knowledge about CRC and colorectal tests, attitude towards CRC and respondentaction regarding CRC. More than half of Malay participants (total n=187) were female (57.2%) and 36.9% of them were working as professionals. Results: The majority of the participants (93.6%) never had a CRC screening test. The study found that only 10.2% of the study participants did not consider that their chances of getting CRC were high. A high percentage of the participants (43.3%) believed that they would have good chance of survival if the cancer would be found early. About one third of the respondents did not want to do screening because of fear of cancer, and concerns of embarrassment during the procedure adversely affected attitude to CRC screening as well. Age, gender, income, family history of CRC, vegetable intake and physical activity were found to be significant determinants of knowledge on CRC. Conclusions: The major barriers identified towards CRC screening identified in our study were fear of pain and embarrassment. The findings have implications for understanding of similarities and differences in attitude to CRC amongst elderly patients in other cultural/geographic regions.

• Journal of the Korean Society for Railway
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• v.8 no.1
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.