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I/O 트랜지스터의 핫 캐리어 주입 개선에 관한 연구

A study on the Hot Carrier Injection Improvement of I/O Transistor

  • 문성열 (전남대학교 전기및반도체공학과) ;
  • 강성준 (전남대학교 전기및반도체공학과) ;
  • 정양희 (전남대학교 전기및반도체공학과)
  • 투고 : 2014.06.25
  • 심사 : 2014.08.11
  • 발행 : 2014.08.31

초록

반도체 소자 제조에서 비용 절감을 위한 공정기술의 스케일링 가속화 경향에 따라 축소기술에 대한 요구가 증가되고 있다. 축소에 따른 또 다른 가장 큰 문제점의 하나는 Hot Carrier Injection (HCI) 특성의 열화이다. 이는 축소 과정에서 생기는 불가피한 가장 큰 이슈중의 하나이며, 특히 입출력 소자에 있어 극복하기 어려운 부분이다. 이의 개선을 위해 유효 채널 길이를 늘이고자 LDD 임플란트 공정 이전에 산화막이 추가되었고, 또한 I/O LDD 임플란트 공정의 이온 입사 각도를 최적화함으로써, LDD 영역에서 E-field 열화 없이 HCI 규격을 만족할 수 있었다.

As the scaling trend becomes accelerated in process technology for cost reduction in semiconductor chip manufacturing, the requirement for shrink technology has increased. Hot Carrier Injection (HCI) degradation for I/O transistors is most concerning part when shrink. To solve this, the effective channel length (Leff) was increased using liner oxide before Light Doped Drain (LDD) implants and optimized the tilt angle to increase Leff without E-field degradation in LDD region, satisfying the HCI specification.

키워드

참고문헌

  1. R. R. Troutman, "VLSI limitation from drain-induced barrier lowering," IEEE Trans. Electron Devices, vol. ED-26, no. 4, 1979, pp. 461-468.
  2. Z. H. Liu, H. Chennming, J. H. Huang, T. Y. Chan, J. MIn-Chie, P. K. Ko and Y. C. Cheng, "Threshold Voltage Model For Deep-Submicrometer MOSFETs," IEEE Trans. Electron Devices. vol. 40, no. 1, 1993, pp. 86-95. https://doi.org/10.1109/16.249429
  3. H. J. Chung, "5-TFT OLED Pixel Circuit Compensating Threshold Voltage Variation of p-channel Poly-Si TFTs," J. of the Korea Institute of Electronic Communication Sciences, vol. 9, no. 3, 2014, pp. 279-284. https://doi.org/10.13067/JKIECS.2014.9.3.279
  4. H. J. Chung, "A Voltage Programming AMOLED Pixel Circuit Compensating Threshold Voltage Variation of n-channel Poly-Si TFTs," J. of The Korea Institute of Electronic Communication Sciences, vol. 8, no. 2, 2013, pp. 207-212. https://doi.org/10.13067/JKIECS.2013.8.2.207
  5. T. Hori, J. Hirase, Y. Odake, and T. Yasui, "Deep-Submicrometer Large - Angle - Tilt Implanted Drain(LATID) Technology," IEEE Trans. Electron. Devices. vol. 39 no. 10, 1992, pp. 2312-2324. https://doi.org/10.1109/16.158803
  6. T. Kuroi, S. Shimizu, A. Furukawa, S. Komori, Y. Kawasaki, S. Kusunoki, Y. Okumura, M. Inuishi, N. Tsubouchi, and K. Horie, "Highly Reliable 0.15${\mu}m$ MOSFETs with Surface Eroximity Gettering (SPG) and Nitrided Oxide Spacer Using Nitrogen Implantation," VLSI Symp. Tech. Dig. Kyoto, Japan, June 1995, pp. 19-20.
  7. P. A. Stolk, H.-J. Gossmann, D. J. Eaglesham, D. C. Jacobson, C. S. Rafferty, G. H. Gilmer, M. Jaraiz, J. M. Poate, H. S. Luftman, and T. E. Haynes, "Physical mechanism of Transient enhanced dopant diffusion in ion-implanted silicon," J. of Applied Physics, vol. 81, no. 9, 1997, pp. 6031-6050. https://doi.org/10.1063/1.364452
  8. R. Bellens, P. Habas, G. Groeseneken, H. E. Maes, J. P. Mieville, G. van den bosch, and L. Deferm, "Analysis and optimisation of the hot-carrier degradation performance of 0.35${\mu}m$ fully overlapped LDD devices," Reliability Physics Symposium, 1995. 33rd Annual Proceedings, IEEE International, Las Vegas, NV, Apr. 1995, pp. 254-259.
  9. M. C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETs," Ph.D Dissertation, Univ. of California, Berkeley, 1990.
  10. Y. Tsividis, "Analysis and Design of Analog Integrated Circuits," Solid-State Circuits Magazine, IEEE, vol. 6, no. 1, 2014, pp. 37-38. https://doi.org/10.1109/MSSC.2013.2289597
  11. C. G. Sodini, P.-K. Ko, and J. L. Moll, "The effect of high field on MOS device and circuit performance" IEEE Trans. Electron Devices, vol. 31, no. 10, 1984, pp. 1386-1393. https://doi.org/10.1109/T-ED.1984.21721