• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1227-1232
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1475-1477
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• 1997

We have fabricated a novel LDD structured polysilicon thin film transistor with a simple fabrication process, compared with the conventional LDD poly-Si TFT, without LDD implantation by employing taper etched $SiO_2$ film instead of LDD implant mask. The leakage current of the novel LDD device is reduced significantly in OFF state while keeping the ON current to be almost identical to that of the non-LDD poly-Si TFTs.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.847-852
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• 2014

As the scaling trend becomes accelerated in process technology for cost reduction in semiconductor chip manufacturing, the requirement for shrink technology has increased. Hot Carrier Injection (HCI) degradation for I/O transistors is most concerning part when shrink. To solve this, the effective channel length (Leff) was increased using liner oxide before Light Doped Drain (LDD) implants and optimized the tilt angle to increase Leff without E-field degradation in LDD region, satisfying the HCI specification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.97-98
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• 2006

For high performance transistor in the 0.14um generation, high speed sram is using a weak region of SCE(Short Channel Effect). It causes serious SCE problem (Vth Roll-Off and Punch-Through etc). This paper shows improvement of Vth roll-off and Ion/Ioff characteristics through high concentration Pocket implant, LDD(Light Dopped Dram) and low energy Implant to reduce S/D Extension resistance. We achieve stabilized Vth and Improved transistor Ion/Ioff performance of 10%.

• The Journal of Advanced Prosthodontics
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• v.9 no.3
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• pp.224-231
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• 2017

PURPOSE. This study was designed to evaluate the teeth and dental implants during dental maintenance therapy over 3 years in different conditions after periodontal and dental prosthetic treatment. MATERIALS AND METHODS. 166 patients received maintenance therapy. 59 patients were treated with 2% minocycline-HCl ointment as local drug delivery (LDD) (L group) and 107 patients were treated without LDD (NL group). Clinical data was collected in maintenance period for evaluation. Patients were classified into groups depending on the application of LDD with maintenance therapy, the type of dental treatment before maintenance period (Pre-Tx), the frequency (F-MT), and regularity (R-MT) of maintenance therapy. RESULTS. The numbers of lost teeth (N-teeth, P=.003) and newly placed dental implants (N-implants, P=.022) are significantly different according to Pre-Tx. F-MT among patients who received surgical dental treatment before maintenance period showed statistical differences in N-teeth (P=.041), but not in N-implants (P=.564). All of the patients in L group showed high F-MT (F-MT1). In NL group, there were no statistical differences in N-teeth or N-implants according to F-MT or R-MT. In F-MT1 group, application of LDD made N-teeth significantly different from both Pre-Tx groups while no significant difference could be found in N-implant. Independent t-test and one-way ANOVA were selected for statistical analysis. CONCLUSION. The regular maintenance therapy and LDD can be effective for teeth during maintenance period. It is not only pharmacological efficacy in decreasing bacterial species that makes LDD a useful adjunct. Application of LDD also motivates patients to take adequate check-ups in the aspects of both frequency and regularity.

• Journal of Periodontal and Implant Science
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• v.27 no.4
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• pp.701-722
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• 1997

It was reported that low dose doxycycline(LDD) regimen could inhibit pathologically elevated collagenase activity in the gingival crevicular fluid of petients with adult periodontitis without producing typical antibiotic side effects. The purpose of this study was to evaluate the effects of LDD regimen(20mg) administered during non-surgical therapy on clinical index and gingival crevicular fluid enzyme activity in diabetics who are at high risk for periodontal disease. Forty-nine subjects having at least two sites with probing pocket depths greater than 4mm were selected. In this double-blind, placebo-controlled study, the patients were administered 20 mg doxycycline capsule or placebo capsule b.i.d. for 2 weeks. Clinical parameters of dental plaque, gingival inflammation, probing pocket depth and probing attachment level were assessed at week 0, 2, 4, and 8. Gingival crevicular fluid samples were collected at the same time to evaluate the activities of collagenase and elastase. Clinical parameters and elastase activity were significantly reduced in all groups compared to the baseline value after treatment. Significantly greater reduction in pocket depth and gain in attachment level was shown in the LDD-administered group compared to placebo group in both adult periodontitis and diabetic patients. Total collagenase activity was also reduced significantly in all groups after treatment, but the greater reduction was seen in the LDD-administered diabetics group compared to relevant placebo group(at 4, 8week). Significantly greater reduction in active collagenase activity was also seen in the LDD-administered group compared to placebo group in diabetic patients(at 2, 4, 8week). These results indicated that use of low dose doxycycline could be aueseful adjunct to instrumentation therapy in the management of diabetic patient with periodontitis as well as adult periodontitis patient.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Journal of IKEEE
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• v.26 no.3
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• pp.422-429
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• 2022

A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuse OTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logic devices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three masks which are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And since the 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. In addition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, which is a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied through the PMOS power switching circuit after packaging, so that the number of package pins can be reduced.