Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Surface Analysis of Aluminum Bonding Pads in Flash Memory Multichip Packaging

  • Son, Dong Ju (Department of Electronic Engineering, Myongji University) ;
  • Hong, Sang Jeen (Department of Electronic Engineering, Myongji University)
  • Received : 2013.12.11
  • Accepted : 2014.06.02
  • Published : 2014.08.25
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Abstract

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.

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References

  1. N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Z. X. Wu, Y.Rui, L. Ebin, Ranganathan, T. Chai, V. Kripesh and J. Lau, IEEE Proc. ECTC (FL, 550, 2008). [DOI: http://dx.doi.org/10.1109/ECTC.2008.4550027].
  2. M. Karnezos, US Patent, 20060138649 A1 (2006).
  3. K. Lee and S. Hong, US Patent, 7,781,325 B2 (2010).
  4. K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbocker, IBM. J. Res. & Dev., 52, 611 (2008). [DOI: http://dx.doi.org/10.1147/JRD.2008.5388567].
  5. M. Karnezos, IEEE IEMT, 64 (2004) [DOI: http://dx.doi.org/10.1109/IEMT.2004.1321633].
  6. EIA/JEDX22-B116, JEDEC, Solid State Technology Division, Electronic Industries Alliance (Arlington, VA, 1998).
  7. R. J. Coyle, A. J. Serafino, and P. P. Solan, Proc. 27th IEEE/SEMI Int. Elect. Manufac. Tech. Symp., (San Francisco, CA, 2002). [DOI: http://dx.doi.org/10.1109/IEMT.2002.1032754].
  8. G. Y. Clatterbaugh, J. A. Weiner, and H. K. Charles, Jr., IEEE Trans. TCHMT, 7, 349 (1984). [DOI: http://dx.doi.org/10.1109/TCHMT.1984.1136367].
  9. Physical Electronics, http://www.phi.com/surface-analysisapplications/semiconductor.html.
  10. C. Jones, W. Crane, R. L. Gilchrist, and R. C. Langley, US Patent, US005380401 A (1995).
  11. S. H. Hong, W. Y. Choi, J. Park, and S. Hong, Trans. Electr. Electron. Mater., 10, 71 (2009). https://doi.org/10.4313/TEEM.2009.10.3.071

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  1. Crystalline defect formation on aluminum bond pads during CMOS wafer storage and process strategies for defect elimination vol.36, pp.3, 2018, https://doi.org/10.1116/1.5027149