Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
권호 표지

Design of an Area-efficient DCME Algorithm for High-speed Reed-Solomon Decoder

고속 Reed-Solomon 복호기를 위한 면적 효율적인 DCME 알고리즘 설계

  • Kang, Sung Jin (School of EEC Engineering, Korea University of Technology and Education)
  • 강성진 (한국기술교육대학교 전기전자통신공학부)
  • Received : 2014.11.04
  • Accepted : 2014.11.28
  • Published : 2014.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

Keywords

References

  1. S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2004
  2. H. Shao, T. Truong, L. Deutsch, J. Yuen, I. Reed, "A VLSI design of a Pipeline Reed-Solomon Decoder," IEEE Trans. on Computers, Vol.c-34, No.5, pp.393-403, May 1985. https://doi.org/10.1109/TC.1985.1676579
  3. Hanho Lee, "High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder," IEEE Trans. on VLSI Systems, Vol.11, No.2, pp.288-294, April 2003. https://doi.org/10.1109/TVLSI.2003.810782
  4. J. H. Baek and M. H. SunWoo, "New degree computationless modified Euclid's algorithm and architecture for Reed-Solomon decoder," IEEE Trans. Very Large Integr. (VLSI) Syst., Vol. 14, No. 8, pp 915-920, Aug. 2006. https://doi.org/10.1109/TVLSI.2006.878484
  5. J. H. Baek and M. H. SunWoo, "Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoders," Electronics Letters, Vol. 43, No. 3, pp. 175-176, Feb. 2007. https://doi.org/10.1049/el:20073718
  6. S. Lee, H. Lee, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Trans. Fundamentals, Vol.E91-A, No.3, pp.830-835, March 2008. https://doi.org/10.1093/ietfec/e91-a.3.830
  7. S. Kang, N. Kim, "Design of Degree-Computationless Modified Euclidean Algorithm using Polynomial Expression," Journal of KICS, Vol.36, No.10, pp.809-815, Oct. 2011. https://doi.org/10.7840/KICS.2011.36A.10.809
  8. Hanho Lee, "A High-Speed Low-Complexity Reed-Solomon Decoder for Optical Communications," IEEE Trans. On Circuits and Systems, Vol.52, No.8, pp.461-465, Aug. 2005. https://doi.org/10.1109/TCSII.2005.850452
  9. H. Ahn, C. Choi, H. Lee, "High-Speed Low-Complexity Folded Degree-Computationless Modified Euclidean Algorithm Architecture for RS Decoders," Proceedings of ISIC '09, pp.582-585, 2009.