• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.7-13
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• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.2 no.1
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• pp.27-39
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• 1998

We describe a fast numerical method for non-separable elliptic equations in self-adjoin form on irregular adaptive domains. One of the most successful results in numerical PDE is developing rapid elliptic solvers for separable EPDEs, for example, Fourier transformation methods for Poisson problem on a square, however, it is known that there is no rapid elliptic solvers capable of solving a general nonseparable problems. It is the purpose of this paper to present an iterative solver for linear EPDEs in self-adjoint form. The scheme discussed in this paper solves a given non-separable equation using a sequence of solutions of Poisson equations, therefore, the most important key for such a method is having a good Poison solver. High performance is achieved by using a fast high-order adaptive Poisson solver which requires only about 500 floating point operations per gridpoint in order to obtain machine precision for both the computed solution and its partial derivatives. A few numerical examples have been presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• Proceedings of the KSME Conference
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• 2001.06e
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• pp.416-421
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• 2001

This paper presents the numerical prediction of sound generated by viscous flow past a circular cylinder. The two dimensional flow field is predicted using FEM based Reynolds-averaged Navier-Stokes solver, and the calculated unsteady fluid field values are utilized by an acoustic code that implements Ffowcs Willianms-Hawkings(FW-H) equation. The integration surface used in acoustic analysis is extended from the cylinder surface to permeable surfaces. The 2D based CFD calculations overpredict the acoustic amplitude, however, if adequate correlation length is used, the predicted acoustic amplitude agrees well with experiment. The predictions using extended integral surface in FW-H equation show results that contain the characteristics of quadrupole - volume integration - noise term, and do not vary seriously with the integral surface location.

• International Journal of Aerospace System Engineering
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• v.2 no.2
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• pp.67-72
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• 2015

The main concern of this study is to integrate the EARSM into an industrial RANS solver in conjunction with the $k-{\omega}$ model, as proposed by Hellsten (EARSMKO2005). In order to improve the robustness, particular limiters are introduced to turbulent conservative variables, and a suitable full-approximation storage (FAS) multi-grid (MG) strategy is designed to incorporate turbulence model equations. The present limiters and MG strategy improve both robustness and efficiency significantly but without degenerating accuracy. Two discretization approachs for velocity gradient on cell interfaces are implemented and compared with each other. Numerical results of a three-dimensional supersonic square duct flow show that the proper discretization of velocity gradient improves the accuracy essentially. To assess the capability of the resulting EARSM $k-{\omega}$ model to predict complex engineering flow, the case of Common Research Model (CRM, Wing-Body) is performed. All the numerical results demonstrate that the resulting model performs well and is comparable to the standard two-equation models such as SST $k-{\omega}$ model in terms of computational effort, thus it is suitable for industrial applications.

• Nuclear Engineering and Technology
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• v.49 no.6
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• pp.1310-1317
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• 2017

GASFLOW-MPI is a widely used scalable computational fluid dynamics numerical tool to simulate the fluid turbulence behavior, combustion dynamics, and other related thermal-hydraulic phenomena in nuclear power plant containment. An efficient scalable linear solver for the large-scale pressure equation is one of the key issues to ensure the computational efficiency of GASFLOW-MPI. Several advanced Krylov subspace methods and scalable preconditioning methods are compared and analyzed to improve the computational performance. With the help of the powerful computational capability, the large eddy simulation turbulent model is used to resolve more detailed turbulent behaviors. A backward-facing step flow is performed to study the free shear layer, the recirculation region, and the boundary layer, which is widespread in many scientific and engineering applications. Numerical results are compared with the experimental data in the literature and the direct numerical simulation results by GASFLOW-MPI. Both time-averaged velocity profile and turbulent intensity are well consistent with the experimental data and direct numerical simulation result. Furthermore, the frequency spectrum is presented and a -5/3 energy decay is observed for a wide range of frequencies, satisfying the turbulent energy spectrum theory. Parallel scaling tests are also implemented on the KIT/IKET cluster and a linear scaling is realized for GASFLOW-MPI.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2286-2292
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• 2008

In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.