전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제50권5호
  • /
  • Pages.67-74
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  • 2013
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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0.18 ㎛ CMOS 공정을 이용한 저 전력 1 Ms/s 12-bit 2 단계 저항 열 방식 DAC

A Low-Power 1 Ms/s 12-bit Two Step Resistor String Type DAC in 0.18 ㎛ CMOS Process

  • 유명섭 (성균관대학교 정보통신대학) ;
  • 박형구 (성균관대학교 정보통신대학) ;
  • 김홍진 (성균관대학교 정보통신대학) ;
  • 이동수 (성균관대학교 정보통신대학) ;
  • 이성호 (한국전자부품연구원) ;
  • 이강윤 (성균관대학교 정보통신대학)
  • Yoo, MyungSeob (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Park, HyungGu (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, HongJim (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, DongSoo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, SungHo (Korea Electronics Technology Institute) ;
  • Lee, KangYoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2013.02.18
  • 발행 : 2013.05.25
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초록

본 논문은 무선 센서분야를 위한 1MS/s rate의 저 전력 12-bit 2단계 저항 열 DAC를 제시하고 있다. 2단계 저항 열 구조를 채택함으로써 복잡함을 줄이고, 소비 전력을 최소화 하고 변환속도를 증가 시킬 수 있었다. 이 칩은 $0.18{\mu}m$ CMOS 공정에서 제작 되었으며, Die 면적은 $0.76{\mu}m{\times}0.56{\mu}m$ 이다. 1.8V의 공급 전압으로부터 측정된 전력 소비는 1.8 mW 이다. 샘플링 주파수가 1MHz 이하에서 측정된 동적 동작범위(Spurious-Free Dynamic Range: SFDR)은 70dB 이다.

A low-power 12-bit resistor string DAC for wireless sensor applications is presented. Two-step approach reduces complexity, minimizes power consumption and area, and increases speed. This chip is fabricated in 0.18-${\mu}m$ CMOS and the die area is $0.76mm{\times}0.56mm$. The measured power consumption is 1.8mW from the supply voltage of 1.8V. Measured SFDR(Spurious-Free Dynamic Range) is 70dB when the sampling frequency is less than 1 MHz.

키워드

참고문헌

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