Transactions on Electrical and Electronic Materials

  • 제12권5호
  • /
  • Pages.197-199
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  • 2011
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Direct Current (DC) Bias Stress Characteristics of a Bottom-Gate Thin-Film Transistor with an Amorphous/Microcrystalline Si Double Layer

  • Jeong, Tae-Hoon (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Si-Joon (School of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Hyun-Jae (School of Electrical and Electronic Engineering, Yonsei University)
  • 투고 : 2011.03.29
  • 심사 : 2011.06.28
  • 발행 : 2011.10.25
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초록

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

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