JSTS:Journal of Semiconductor Technology and Science

  • 제10권3호
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  • Pages.232-239
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  • 2010
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

  • Jung, Hae-Kang (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Lee, Soo-Min (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Sim, Jae-Yoon (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Park, Hong-June (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH))
  • 투고 : 2010.08.19
  • 심사 : 2010.09.27
  • 발행 : 2010.09.30
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초록

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

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참고문헌

  1. K. Lee, et al., “A Serpentine Guard Trace toReduce the Far-End Crosstalk Voltage and theCrosstalk Induced Timing of Parallel MicrostripLines,” IEEE Transactions on AdvancedPackaging, Vol.31, No.4, pp.809-817, Nov., 2008. https://doi.org/10.1109/TADVP.2008.924226
  2. K. Lee, et al., “Serpentine Guard Trace to ReduceFar-end Crosstalk and Even-Odd Mode VelocityMismatch of Microstrip Lines by More than 40%,”ECTC, 2007, pp.329-332.
  3. K. Lee, et al., “Serpentine Microstrip Lines withZero Far-End Crosstalk for Parallel High-SpeedDRAM Interfaces,” IEEE Transactions onAdvanced Packaging, Vol.33, No.3, pp.552-558,May, 2010. https://doi.org/10.1109/TADVP.2009.2033938
  4. S.K. Lee, et al., “FEXT-eliminated stub-alternatedmicrostrip line for multi-gigabit/second parallellinks,” Electronics Letters, Vol.44, No.4, Feb.,2008, pp.272-273. https://doi.org/10.1049/el:20083043
  5. D.G. Kam, et al., “A New Twisted DifferentialLine Structure on High-Speed Printed CircuitBoards to Enhance Immunity to Crosstalk andExternal Noise,” IEEE Microwave and WirelessComponents Letters, Vol.13, No.9, Sep., 2003. https://doi.org/10.1109/LMWC.2003.815181
  6. H.K. Jung, et al., “A 4 Gb/s 3-bit ParallelTransmitter With the Crosstalk-Induced JitterCompensation Using TX Data Timing Control,”IEEE Journal of Solid State Circuits, Vol.44,No.11, pp.2891-2900, Nov., 2009. https://doi.org/10.1109/JSSC.2009.2028917
  7. J. F. Buckwalter, et al., “Cancellation of Crosstalk-Induced Jitter,” IEEE Journal of Solid StateCircuits, Vol.41, No.3, Mar., 2006, pp.621-632. https://doi.org/10.1109/JSSC.2005.864113
  8. K-I. Oh, et al., “A 5-Gb/s/pin Transceiver for DDRMemory Interface with a Crosstalk SuppressionScheme,” IEEE J. Solid-State Circuits, Vol.44,No.8, pp.2222-2232, Aug., 2009. https://doi.org/10.1109/JSSC.2009.2022303

피인용 문헌

  1. A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface vol.46, pp.9, 2011, https://doi.org/10.1109/JSSC.2011.2136590
  2. A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines vol.47, pp.9, 2012, https://doi.org/10.1109/JSSC.2012.2197233