한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제34권7A호
  • /
  • Pages.568-573
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  • 2009
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  • 1226-4717(pISSN)
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  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
권호 표지

온칩 시동회로를 갖는 CMOS DC-DC 벅 변환기 설계

Design of monolithic DC-DC Buck converter with on chip soft-start circuit

  • 박승찬 (삼성전자LSI) ;
  • 임동균 (인하대학교 전자공학과 아날로그 적접회로 설계 연구실) ;
  • 이상민 (인하대학교 전자공학과) ;
  • 윤광섭 (인하대학교 전자공학과)
  • 발행 : 2009.07.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서 0.13um CMOS 공정으로 설계된 배터리 기반 휴대용 통신 시스템 구동용의 온칩 시동회로를 갖는 스텝다운 CMOS DC-DC 변환기를 제안하였다. 1MHz의 스위칭 주파수를 기반으로 설계된 벅 변환기에는 온칩 시동회로와 커패시터 멀티플라이어 기법을 이용한 보상회로를 포함시켰다. 칩 측정 결과 2.5V ${\sim}$3.3V의 입력 전압을 1.2V로 강압시키는데 최대 87.2%의 효율을 갖는다. 최대 부하 전류, 출력 전류 리플 및 전압 리플은 각각 500mA, 25mA, 24mV 이다.

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

키워드

참고문헌

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