Journal of the Korea Society for Simulation (한국시뮬레이션학회논문지)

The Korea Society for Simulation (한국시뮬레이션학회)
권호 표지
DOI QR코드

DOI QR Code

RRAM (Redundant Random Access Memory) Spare Allocation in Semiconductor Manufacturing for Yield Improvement

수율향상을 위한 반도체 공정에서의 RRAM (Redundant Random Access Memory) Spare Allocation

  • 한영신 (성균관대학교 반도체 시스템 공학과)
  • Received : 2009.08.05
  • Accepted : 2009.11.02
  • Published : 2009.12.30
Download PDF
⟨ Previous Next ⟩

Abstract

This has been possible by integration techniques such as very large scale integration (VLSI) and wafer scale integration (WSI). Redundancy has been extensively used for manufacturing memory chips and to provide repair of these devices in the presence of faulty cells. If there are too many defects, the momory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is nedded for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The proposed CRA (Correlation Repair Algorithm) simulation, beyond the idea of the conventional redundancy analysis algorithm, aims at reducing the time spent in the process and strengthening cost competitiveness by performing redundancy analysis after simulating each case of defect.

VLSI(Very Large Scale Integration)와 WSI(Wafer Scale Integration)와 같은 통합기술로 인해 큰 용량의 메모리 대량생산이 가능 하게 된 지금 Redundancy는 메모리 칩의 제조와 결함이 있는 셀을 지닌 디바이스를 치료하는데 광범위하게 사용되어져왔다. 메모리칩의 밀도가 증가함에 따라 결함의 빈도 또한 증가한다. 많은 결함이 있다면 어쩔 수 없겠지만 적은 결함이 발생한 경우에는 해당 다이를 reject 시키는 것 보다는 수선해서 사용하는 것이 메모리생산 업체 입장에서는 보다 효율적이고 원가 절감 차원에서 필수적이다. 이와 같은 이유로 laser repair라는 공정이 필요하고 laser repair공정의 정확한 타깃을 설정하기 위해 redundancy analysis가 필요하게 되었다. CRA시뮬레이션은 기존의 redundancy analysis 알고리즘의 개념에서 벗어나 결함 유형별로 시뮬레이션한 후 RA를 진행함으로써 RA에 소요되는 시간을 절약함으로써 원가 경쟁력 강화를 할 수 있다.

Keywords

References

  1. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, and Cheng- Wen Wu, "A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories", Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
  2. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin. A built-in self-test and selfdiagnosis scheme for embedded SRAM. In Proc. Ninth IEEE Asian Test Symp. (ATS), pages 45-50, Taipei, Dec. 2000.
  3. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu. Error catch and analysis for semiconductor memories using March tests. In Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), pages 468–471, San Jose, Nov. 2000.
  4. R. Rajsuman, "Design and test of large embedded memories", an overview, IEEE Design & Test of Computers, 2001, pp. 16-27.
  5. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, "Built-In Redundancy Analysis for Memory Yield Improvement" IEEE TRANSACTIONS ON RELIABILITY, Vol. 52, No. 4, DECEMBER 2003.
  6. Shyue-Kung Lu and Chih-Hsien Hsu, "Fault Tolerance Techniques for High Capacity RAM", IEEE TRANSACTIONS ON RELIABILITY, Vol. 55, No. 2, JUNE 2006
  7. Kawagoe, T., et al.: 'A built-in self-repair analyzer (CRESTA) for embedded DRAMs'. Proc. 2000 Test Conf., ITC, Atlantic city, NJ, USA, 2000, pp. 567–573
  8. Huang, C.-T., Wu, C.-F., Li, J.-F., and Wu, C.-W.: 'Builtin redundancy analysis for memory yield improvement', IEEE Trans. Reliab., 2003, 52, (4), pp. 386-399 https://doi.org/10.1109/TR.2003.821925
  9. Y. Zorian and S. Shoukourian, ''Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield,'' IEEE Design & Test, Vol. 20, No. 3, May-June 2003, pp. 58-66.
  10. R.-F. Huang et al., ''A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories,'' Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 02), IEEE CS Press, 2002, pp. 68-73.
  11. C.-T. Huang et al., ''Built-in Redundancy Analysis for Memory Yield Improvement,'' IEEE Trans. Reliability, Vol. 52, No. 4, Dec. 2003, pp. 386-399. https://doi.org/10.1109/TR.2003.821925
  12. C.-F. Wu et al., ''Fault Simulation and Test Algorithm Generation for Random Access Memories,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 4, Apr. 2002, pp. 480-490. https://doi.org/10.1109/43.992771
  13. T.J. Bergfeld, D. Niggemeyer, and E.M. Rudnick, ''Diagnostic Testing of Embedded Memories Using BIST,'' Proc. Design, Automation and Test in Europe Conf. (DATE 00), IEEE CS Press, 2000, pp. 305-309.