• Journal of Information Technology Applications and Management
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• v.15 no.1
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• pp.243-260
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• 2008

To prevent low yields in the semiconductor industry is crucial to the success of that industry. However, to prevent low yields is difficult because of too many factors to affect yield variation and their complex relation in the semiconductor manufacturing process. This study presents a new efficient detection methodology for detecting abnormal yields including high and low yields, which can forecast the yield level of a production unit (namely a lot) based on yield-related feature variables' behaviors. In the methodology, we use C5.0 to identify the yield-related feature variables that are the combination of correlated process variables associated with yield, use SOM (Self-Organizing Map) neural networks to extract and classify significant patterns of past abnormal yield lots and finally use C5.0 to generate classification rules for detecting abnormal yield lot. We illustrate the effectiveness of our methodology using a semiconductor manufacturing company's field data.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.168-173
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• 2022

As the function of a product is advanced and the process is refined, the yield in the fine manufacturing process becomes an important variable that determines the cost and quality of the product. Since a fine manufacturing process generally produces a product through many steps, it is difficult to find which process or equipment has a defect, and thus it is practically difficult to ensure a high yield. This paper presents the system architecture of how to build a smart manufacturing system to analyze the big data of the manufacturing plant, and the equipment factor analysis methodology to increase the yield of products in the smart manufacturing system. In order to improve the yield of the product, it is necessary to analyze the defect factor that causes the low yield among the numerous factors of the equipment, and find and manage the equipment factor that affects the defect factor. This study analyzed the key factors of abnormal equipment that affect the yield of products in the manufacturing process using the data mining technique. Eventually, a methodology for finding key factors of abnormal equipment that directly affect the yield of products in smart manufacturing systems is presented. The methodology presented in this study was applied to the actual manufacturing plant to confirm the effect of key factors of important facilities on yield.

• IE interfaces
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• v.22 no.3
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• pp.252-262
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• 2009

It is crucial to prevent low yields in the semiconductor industry. Since many factors affect variation in yield and they are deeply related, preventing low yield is difficult. There have been substantial researches in the field of yield prediction. Many researchers had used the statistical methods. Many studies have shown that artificial neural network (ANN) achieved better performance than traditional statistical methods. However, despite ANN's superior performance some problems such as over-fitting and poor explanatory power arise. In order to overcome these limitations, a relatively new machine learning technique, support vector machine (SVM), is introduced to classify the yield. SVM is simple enough to be analyzed mathematically, and it leads to high performances in practical applications. This study presents a new efficient classification methodology, Stepwise-SVM (SSVM), for detecting high and low yields. SSVM is step-by-step adjustment of parameters to be precisely the classification for actual high and low yield lot. The objective of this paper is to examine the feasibility of SVM and SSVM in the yield classification. The experimental results show that SVM and SSVM provides a promising alternative to yield classification for the field data.

• IE interfaces
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• v.21 no.2
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• pp.151-160
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• 2008

Defect size distribution is a probability density function for the defects that occur on wafers or glasses during semiconductor/LCD fabrication. It is one of the most important information to estimate manufacturing yield using well-known statistical estimation methods. The defects are detected by automatic optical inspection (AOI) facilities. However, the data that is provided from AOI is not accurate due to resolution of AOI and its defect detection mechanism. It causes distortion of defect size distribution and results in wrong estimation of the manufacturing yield. In this paper, I suggest a size conversion method and a maximum likelihood estimator to overcome the vague defect size information of AOI. The methods are verified by the Monte Carlo simulation that is constructed as similar as real situation.

• Journal of Korean Society for Quality Management
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• v.47 no.4
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• pp.725-737
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• 2019

Purpose: We used a data analysis method to improve semiconductor manufacturing yield. We defined and optimized important factors and applied our findings to a real-world process. The semiconductor industry is very cost-competitive; our findings are useful. Methods: We collected data on 15 independent variables and one dependent variable (yield); we removed outliers and missing values. Using SPSS Modeler ver. 18.0, we analyzed the data both continuously and discretely and identified common factors. Results: We optimized two independent variables in terms of process conditions; yield improved. We used DS Leak software to model netting and Contact CD software to model meshes. DS Leak shows smaller the better characterisrics and Contact CD shows normal the best characteristics Conclusion: Various efforts have been made to improve semiconductor manufacturing yields, and many studies have created models or analyzed various characteristics. We not only defined important factors but also showed how to control processing to improve semiconductor yield.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.3
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• pp.154-163
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• 2010

Process monitoring of output variables affecting final performance have been mainly executed in semiconductor manufacturing process. However, even earlier detection of causes of output variation cannot completely prevent yield loss because a number of wafers after detecting them must be re-processed or cast away. Semiconductor manufacturers have put more attention toward monitoring process inputs to prevent yield loss by early detecting change-point of the process. In the paper, we propose the method to efficiently monitor functional input variables in multi-phase semiconductor manufacturing process. Measured input variables in the multi-phase process tend to be of functional structured form. After data pre-processing for these functional input data, change-point analysis is practiced to the pre-processed data set. If process variation occurs, key variables affecting process variation are selected using contribution plot for monitoring efficiency. To evaluate the propriety of proposed monitoring method, we used real data set in semiconductor manufacturing process. The experiment shows that the proposed method has better performance than previous output monitoring method in terms of fault detection and process monitoring.

• International Journal of Quality Innovation
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• v.7 no.2
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• pp.141-156
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• 2006

This study describes a novel algorithm for optimizing the quality yield of silicon wafer slicing. 12 inch wafer slicing is the most difficult in terms of semiconductor manufacturing yield. As silicon wafer slicing directly impacts production costs, semiconductor manufacturers are especially concerned with increasing and maintaining the yield, as well as identifying why yields decline. The criteria for establishing the proposed algorithm are derived from a literature review and interviews with a group of experts in semiconductor manufacturing. The modified Delphi method is then adopted to analyze those results. The proposed algorithm also incorporates the analytic hierarchy process (AHP) to determine the weights of evaluation. Additionally, the proposed algorithm can select the evaluation outcomes to identify the worst machine of precision. Finally, results of the exponential weighted moving average (EWMA) control chart demonstrate the feasibility of the proposed AHP-based algorithm in effectively selecting the evaluation outcomes and evaluating the precision of the worst performing machines. So, through collect data (the quality and quantity) to judge the result by AHP, it is the key to help the engineer can find out the manufacturing process yield quickly effectively.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• IE interfaces
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• v.23 no.3
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• pp.205-212
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• 2010

The learning curve model is a mathematical form which represents the relationship between the manufacturing experience and its effectiveness. The semiconductor manufacturing is widely known as an appropriate example for the learning effect due to its complicated manufacturing processes. In this paper, I propose a new compound learning curve model for semiconductor products in which the general learning curve model and the growth curve are composed. The dependent variable and the effective independent variables of the model were abstracted from the existing learning curve models and selected according to multiple regression processes. The simulation results using the historical DRAM data show that the proposed compound learning curve model is one of adequate models for describing learning effect of semiconductor products.