Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Development of Digital Controller and Monitoring System for UPS Inverter

UPS 인버터의 디지털 제어기 및 모니터링 시스템의 개발

  • Park, Jee-Ho (Dept. of Mechatronics Engineering, Tongmyong University) ;
  • Hwang, Gi-Hyun (Division of Computer Information Engineering, Dongseo University) ;
  • Kim, Dong-Wan (Dept. of Electrical and Electronic Engineering, Tongmyong University)
  • 박지호 (동명대학교 메카트로닉스공학과) ;
  • 황기현 (동서대학교 컴퓨터정보공학부) ;
  • 김동완 (동명대학교 전기전자공학부)
  • Published : 2007.01.25
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

본 논문에서는 UPS 인버터의 성능 개선을 위하여 출력측 LC 필터의 커패시터 전압과 전류의 2중 제어루프를 구성하고, 2중 제어루프에 디지털 제어시스템을 설계하였다. 또한, 디지털 제어기의 연산지연시간을 보상하기 위하여 이러한 연산지연시간을 인버터 플랜트의 고유한 파라미터로 가정하고, 플랜트 모델에 포함시켜 모델링 하였다. UPS 인버터 출력전압의 과도상태 응답특성을 개선하고, 파라미터 변동에 강인한 특성을 얻기 위하여 2중 제어루프에서 내부 전류 제어루프는 내부 모델 제어기를 제안하였다. UPS 인버터 출력전압의 0의 정상상태 오차를 얻기 위하여 외부 전압 제어루프는 비례 제어기와 공진 제어기를 병렬로 연결한 비례-공진 전압제어기를 제안하였다. 또한, 사용자에게 쉽게 UPS의 동작 상태를 표시하기 위하여 그래픽 사용자 인터페이스를 이용한 UPS의 모니터링 시스템을 구현하였다.

Keywords

References

  1. N. M. Abdel-Rahim and J. E. Quaicoe, 'Analysis and Design of a Multiple Feedback Loop Control Strategy for Single-Phase Voltage-Source UPS Inverters,' IEEE Trans. Power Electronics, Vol. 11, no. 4, pp. 532-541, 1996 https://doi.org/10.1109/63.506118
  2. T. Yokoyama and A. Kawamura, 'Disturbance Observer Based Fully Digital Controlled PWM Inverter for CVCF Operation,' IEEE Trans. Power Electronics, Vol. 9, no. 5, pp. 473-480, 1994 https://doi.org/10.1109/63.321031
  3. Y. Ito and S. Kawauchi, 'Microprocessor-Based Robust Digital Control for UPS with Three-Phase PWM Inverter,' IEEE Trans. Power Electronics, Vol. 10, no. 2, pp. 196-204, 1995 https://doi.org/10.1109/63.372604
  4. O. Kukrer, 'Deadbeat Control of a Three-Phase Inverter with an Output LC Filter,' IEEE Trans. Power Electronics, Vol. 11, no. 1, pp. 16-23, 1996 https://doi.org/10.1109/63.484412
  5. O. Kukrer, 'Discrete-Time Current Control of Voltage-Fed Three-Phase PWM Inverters,' IEEE Trans. Power Electronics, Vol. 11, no. 2, pp. 260-269, 1996 https://doi.org/10.1109/63.486174
  6. D. N. Zmood and D. G. Holmes, 'Stational Frame Current Regulation of PWM Inverters with Zero Steady State Error,' IEEE PESC'99, pp. 1185-1190, 1999 https://doi.org/10.1109/PESC.1999.785662
  7. H. Gueldner, H. Wolf, and N. Blacha, 'Single Phase UPS Inverter with Variable Output Voltage and Digital State Feedback Control,' IEEE ISIE'01, pp. 1089-1094, 2001 https://doi.org/10.1109/ISIE.2001.931627